High Density Double and Triple Layer Tantalum Pentoxide Decoupling Capacitors

High-performance integrated circuits (ICs) require extremely low impedance power distribution. The low voltage, high current requirements of these devices must be provided by decoupling capacitors very close to the IC. Currently this decoupling is provided by discrete surface mount capacitors with relatively high parasitic inductance, requiring many devices in parallel to provide low impedance at high frequencies. Thin film, large area tantalum pentoxide (TaO) dielectric capacitors exhibit very low parasitic inductance, but have been limited in capacitance density to 100nF/cm for single layer devices. Multilayer thin film capacitors can substantially increase the available capacitance. These multilayer thin film capacitors can be fabricated in a variety of ways, allowing them to be embedded between FR-4 layers, under ICs, or even embedded in IC packages. We previously described the initial results of two-layer capacitors fabricated on silicon . These devices had two dielectric layers and three copper plates. Recently we extended the technology to three dielectric layers, and fabricated devices with dielectrics as thin as 1000, to yield a total capacitance density of 0.6F/cm. Capacitors were fabricated on silicon wafers by sputtering a metal plate topped with tantalum, and then wet anodizing the tantalum layer. The process was repeated to create a multilayer stack. The stack was then patterned from top to bottom by successive lithographic and etching steps. This paper will describe the fabrication process in detail. Detailed electrical properties for the resulting two and three layer devices, such as capacitance density, leakage current, breakdown voltage, and impedance will be presented. Using the three-layer process, we fabricated devices for inclusion in a 3-D electronic assembly for a DARPA program, and these devices will be described. Screening and test methods to ensure device reliability will be briefly discussed.     

Estimating the noise mitigation effect of local decoupling in printed circuit boards

Local decoupling, i.e., placing decoupling capacitors sufficiently close to device power/ground pins in order to decrease the impedance of power bus at frequencies higher than the series resonant frequency, has been studied using a modeling approach, a hybrid lumped/distributed circuit model established and an expression to quantify the benefits of power bits noise mitigation due to local decoupling developed. In this work, a test board with a local decoupling capacitor was studied and the noise mitigation effect due to the capacitor placed adjacent to an input test port was measured. Closed-form expressions for self and mutual inductances of vias are developed, so that the noise mitigation effect can then be estimated using the previously developed expression. The difference between the estimates and measurements is approximately 1 dB, which demonstrates the application of these closed-form expressions in the PCB power bus designs. Shared-via decoupling, capacitors sharing vias with device power/ground pins, is also modeled as an extreme case of local decoupling.     

Estimating the power bus impedance of printed circuit boards with embedded capacitance

Embedded capacitance is an alternative to discrete decoupling capacitors and is achieved by enhancing the natural capacitance between closely spaced power and return planes. This paper employs a simple cavity model to investigate the features affecting the power bus impedance of printed circuit boards with embedded capacitance.     

Modeling and simulation of integrated capacitors for high frequencychip power decoupling

Power and ground decoupling is typically accomplished using a hierarchy of discrete capacitors spread throughout the power distribution network. Many of the limitations of discrete decoupling capacitors can be overcome with integrated capacitors. A modeling approach for integrated capacitors based on the partial-element-equivalent-circuit (PEEC) formulation is presented. This approach has been applied to 3M C-ply, a flexible planar integrated capacitor technology that can be laminated into multilayer substrates, such as printed wiring boards. The decoupling capability of 3M C-Ply technology for chip power distribution has been compared with conventional surface-mount technology (SMT)     

High dielectric constant thin film EBG power/ground network for broad-band suppression of SSN and radiated emissions

We experimentally demonstrated the great advantages of a high dielectric constant thin film electromagnetic bandgap (EBG) power distribution network (PDN) for the suppression of power/ground noises and radiated emissions in high-performance multilayer digital printed circuit boards (PCBs). Five-layer test PCBs were fabricated and their scattering parameters measured. The power plane noise and radiated emissions were measured, investigated and related to the PDN impedance. This successfully demonstrated that the bandgap of the EBG was extended more than three times, covering a range of hundreds of MHz using a 1-cm /spl times/ 1-cm EBG cell, the SSN was reduced from 170 mV to 10 mV and the radiated emission was suppressed by 22 dB because of the high dielectric constant thin film EBG power/ground network.     

Effective Radii of On-Chip Decoupling Capacitors

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard cell circuit blocks. The efficacy of on-chip decoupling capacitors depends upon the impedance of the power/ground lines connecting the capacitors to the current loads and power supplies. A design methodology for placing on-chip decoupling capacitors is presented in this paper. A maximum effective radius is shown to exist for each on-chip decoupling capacitor. Beyond this effective distance, a decoupling capacitor is ineffective. Depending upon the parasitic impedance of the power distribution system, the maximum voltage drop seen at the current load is caused either by the first droop (determined by the rise time) or by the second droop (determined by the transition time). Two criteria to estimate the minimum required on-chip decoupling capacitance are developed based on the critical parasitic impedance. In order to provide the required charge drawn by the load, the decoupling capacitor has to be charged before the next switching cycle. For an on-chip decoupling capacitor to be effective, both effective radii criteria should be simultaneously satisfied.     

Quantifying SMT decoupling capacitor placement in dc power-busdesign for multilayer PCBs

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach     

音响分频器使用的有机薄膜电容器

音响分频器中使用的有机薄膜电容器 ,其阻抗和损耗频率特性的优劣直接影响分频器的阻抗及功率特性 ,从而影响音响的质量。在选用电容器时 ,应注意 :1选用无感式卷绕的金属化有机薄膜电容器 ,使 LESL趋于零 ;2选用边缘加厚的金属化有机薄膜电容器 ,降低极板电阻、接触电阻和接触损耗 ,改善电容器的阻抗和损耗频率特性 ,满足分频器的阻抗匹配和功率匹配的要求 ;3首选粗短结构的电容器 ;4选用圆形结构电容器 ,避免连续性自愈发生。正确选择优质电容器 ,满足良好的听觉效果。     

Improvements in Noise Suppression for I/O Circuits Using Embedded Planar Capacitors

The performance of embedded planar capacitors in noise suppression of input/output (I/O) circuits and improvements in board impedance profile have been investigated in this paper. Simultaneous switching noise (SSN) is a critical issue in today's systems and this paper shows performance improvements by introducing thin planar embedded capacitors in the board stack up. Measurement and modeling results by including the effects of transmission lines and the power ground plane pairs in the board stack up in the gigahertz range quantify the performance of the embedded capacitors.     

Modeling and transient simulation of planes in electronic packages

This paper presents a modeling and simulation approach for ground/power planes in high speed packages. A plane pair structure is first characterized in terms of its impedance (Z) matrix at arbitrary port locations in the frequency domain. This solution is then extended for multiple plane pairs under the assumption that skin effect is prominent at higher frequencies causing isolation between the layers. Since the solutions are in analytical form, the frequency and transient response can be computed efficiently requiring small computational time. To develop spice models, equivalent circuits are constructed using resonator models with passive elements using model order reduction methods. This paper also discusses a method for incorporating decoupling capacitors into the plane models. The simulation results show good correlation with measured data     

A S-Bridged Inductive Electromagnetic Bandgap Power Plane for Suppression of Ground Bounce Noise

In this letter, a novel power plane using an inductive S-bridged electromagnetic bandgap (EBG) is proposed for ultra wideband suppression of the ground bounce noise. The S-shaped bridge detouring unit cells effectively increase the power plane inductance. -30 dB stopband is realized from 220 MHz to 7 GHz. The stopband lower limit (220 MHz) of the proposed EBG has been greatly reduced from that (550 MHz) of L-bridged EBG. It is expected that the number of local decoupling capacitors for the power plane integrity is reduced using the proposed S-bridged EBG without the self resonance effect.     

Power-bus decoupling with embedded capacitance in printed circuit board design

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).     

Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs

A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE.      

The effect of test system impedance on measurements of groundbounce in printed circuit boards

Based on the 3D-FDTD approach, an efficient equivalent model employing the embedded resistive voltage source is proposed to simulate the effect of test system impedance on the measurement of the ground bounce noise for the power planes structure in the printed circuit boards (PCB). Compared with the measured results by vector network analyzer, this equivalent model well predicts the impedance behavior of the V_cc/GND power planes. The influences of different probe loading conditions of the test system on the measurement of impedance behavior are studied. It is found that the effects of the probing loads on the measurement of the ground bounce noise is significant at the frequencies near the dc point and resonance, but the influences of the probes are small at the frequencies far from resonance. In addition, the transfer characteristics of the power bus in the realistic digital circuits with decoupling capacitance being considered are simulated in the FDTD model. The difference of the transfer behavior between the realistic case without coaxial feed and the measured results with probing effects is also numerically compared. We find that the ground bounce noise in the real circuit can be accurately measured at most frequencies, where the power planes act in very low impedance, except at the frequencies near dc and resonance frequencies, where the power planes behave in relatively higher impedance characteristics     

Embedded resistors and capacitors for organic-based SOP

System-on-package (SOP) architectures take advantage of compact, high-performance designs to place the maximum amount of functionality on a subsystem that can then be mounted on a lower-cost, lower density interconnect board. Embedding passive components is a key technology in achieving these goals since this enables smaller SOP substrate footprints or, equivalently, higher functional density, along with better power distribution, increased design flexibility and improved reliability. The resulting footprint areas of integrating capacitors will have more of an effect on the layer count of SOP assemblies than will integrating resistors due to the rather low specific capacitances of most embeddable dielectrics, but the situation is improving steadily. It may be necessary to use two different dielectric materials to cover the entire required range. The inherently lower parasitic inductance of embedded capacitors makes them much more useful in decoupling than surface mount capacitors, enabling more robust power distribution and decreased power/ground noise. The key to this performance enhancement in large boards is the use of a thin dielectric to decrease the inductance but, for the smaller SOP substrates, the dielectric constant must also be high to provide sufficient decoupling capacitance in the reduced area.     

Integrating High-k Ceramic Thin Film Capacitors into Organic Substrates Via Low-Cost Solution Processing

Current organic package-compatible embedded decoupling capacitors are based on thick film (8-16 m) polymer-ceramic composites with dielectric constant (k) of 20-30 and do not have sufficient capacitance density to meet the impedance requirements for emerging high-speed circuits and high power density microprocessors. High-k/high capacitance density ceramics films that can meet the performance targets are generally deposited by high-temperature processing or costly vacuum technology (radio frequency sputtering, PECVD) which are expensive and also incompatible with organic packages. The objective of this project is to develop ultra thin films (100-300nm) with high dielectric constant using organic compatible processes to meet future decoupling applications. In the current study, direct deposition of crystalline ceramic films on organic boards at temperatures less than 100C was demonstrated with the hydrothermal method. Post-hydrothermal treatments were shown to minimize the defects in the as-synthesized hydrothermal barium titanate films and improve the breakdown voltage (BDV) and leakage characteristics. Thin films with high capacitance densities and breakdown voltages of 10V were demonstrated. As an alternate technique, sol-gel technology was also demonstrated to integrate ceramic thin films in organic packages. A major barrier to synthesis of sol-gel films on copper foils is the process incompatibility of the sol-gel barium titanate with the copper electrodes. To enable process compatibility, process variables like sol pyrolysis temperature and time, and sintering conditions/atmosphere were optimized. Capacitance densities above 1.1F/cm was demonstrated on commercial copper foils with a BDV above 10 V. The two technologies reported in this study can potentially meet midfrequency decoupling requirements of digital systems.     

Power distribution networks for system-on-package: status and challenges

The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.     

Decoupling capacitors for multi-voltage power distribution systems

Multiple power supply voltages are often used in modern high-performance ICs, such as microprocessors, to decrease power consumption without affecting circuit speed. To maintain the impedance of a power distribution system below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy. The system of decoupling capacitors used in power distribution systems with multiple power supplies is described in this paper. The noise at one power supply can propagate to the other power supply, causing power and signal integrity problems in the overall system. With the introduction of a second power supply, therefore, the interaction between the two power distribution networks should be considered. The dependence of the impedance and magnitude of the voltage transfer function on the parameters of the power distribution system is investigated. An antiresonance phenomenon is intuitively explained in this paper. It is shown that the magnitude of the voltage transfer function is strongly dependent on the parasitic inductance of the decoupling capacitors, decreasing with smaller inductance. Design techniques to cancel and shift antiresonant spikes out of range of the operating frequencies are presented. It is also shown that it is highly desirable to maintain the effective series inductance of the decoupling capacitors as low as possible to decrease the overshoots of the response of the dual-voltage power distribution system over a wide range of operating frequencies. A criterion for an overshoot-free voltage response is presented in this paper. It is noted that the frequency range of the overshoot-free voltage response can be traded off with the magnitude of the response.     

Power distribution system design methodology and capacitorselection for modern CMOS technology

Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients     

An experimental procedure for characterizing interconnects to theDC power bus on a multilayer printed circuit board

The effectiveness of DC power bus decoupling is impacted by the inductance associated with interconnect vias in printed circuit boards (PCBs). Adequate characterization of these interconnects is necessary to facilitate modeling and simulation, and to assess the effectiveness of added decoupling. A measurement procedure is presented for determining the series inductance and resistance of an interconnect with a network analyzer. The validity and limitations of the procedure are discussed. Experimental results of interconnect parameters on an 8×10 in ten-layer test-board corroborate those measured with a precision impedance analyzer. The measured interconnect values are used to simulate several cases of power-bus decoupling which show good agreement with two-port swept frequency measurements