The role of the mercury-Si Schottky-barrier height in /spl Psi/-MOSFETs

Pseudo-MOSFETs (/spl Psi/-MOSFET) are routinely used for silicon-on-insulator (SOI) material characterization, allowing threshold voltage, electron and hole mobility, doping density, oxide charge, interface trap density, etc. to be determined. The HgFET, one version of the /spl Psi/-MOSFET, uses mercury source and drain contacts. It is a very effective SOI test structure, but its current-voltage behavior is critically dependent on the Hg-Si interface. We have investigated this interface through current-voltage measurements of HgFETs and Schottky diodes and through device modeling. We show that modest barrier height changes of 0.2 eV lead to current changes of up to three orders of magnitude. Etching the Si surface in a mild HF :H/sub 2/O solution can easily change barrier heights and we attribute this behavior to Si surface passivation of dangling bonds. As this surface passivation diminishes with time, the Si surface becomes a more active generation site and the barrier height of the Hg-Si interface changes, taking on the order of 50-100 h at room temperature in air.     

SOI bulk and surface generation properties measured with the pseudo-MOSFET

The pseudo-MOSFET (/spl Psi/-MOSFET) is an excellent test structure to characterize the quality of SOI films by measuring the generation lifetime without complicated processing steps. We use this simple structure and a modified one to determine the SOI film generation lifetime, the surface generation velocities at the upper and lower interfaces, and the effect of HF and iodine solution surface passivation and hydrogen annealing. The modified /spl Psi/-MOSFET has an additional top gate permitting independent control of top and bottom surface potentials thereby providing the ability to control surface generation through surface accumulation, depletion, or inversion.     

RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate

In this paper, we investigate the impact of a passivation layer on the performance of a commercial high-resistivity (HR) SOI CMOS technology. The passivation layer consists of a 300-nm-thick polysilicon cover located directly below the buried oxide (BOX). Both passive and active devices are studied. It is demonstrated that substrate passivation completely suppresses substrate losses that are usually induced by parasitic surface conduction at the substrate/BOX interface in oxidized HR Si substrates. We also report no effect of the underlying polysilicon on the dc and RF behavior of MOSFETs devices. The results shown here strongly suggest that substrate passivation using polysilicon is a promising tool to eradicate substrate losses in HR SOI wafers, thereby increasing the performance of functional SOI logic and high-speed circuits.     

Low-frequency noise in SOI pseudo-MOSFET with pressure probes

Low-frequency noise (LFN) is generated by interactions of the channel carriers with interface traps and oxide charges. Therefore, noise measurements on silicon on insulator (SOI) wafers can give important information about the state of the interfaces and their defect density. Here, noise measurements at wafer level were performed using the pseudo-MOSFET (Ψ-MOSFET) configuration. 1/f noise behavior in relatively thick and ultra-thin SOI layers is obtained. No probe pressure dependence of the noise is observed. The influence of wafer surface states is showed and further confirmed in passivated SOI samples. Origins of noise generation are discussed.     

Surface passivation of InGaP/InGaAs/GaAs pseudomorphic HEMTs with ultrathin GaS film

We report on the successful surface passivation of wide recess InGaP/InGaAs/GaAs pseudomorphic HEMTs with MBE-grown ultrathin GaS film (2 nm) employing a single precursor, tertiarybutyl-galliumsulfide-cubane ([(t-Bu)GaS]/sub 4/). At the recess length of 1.1 /spl mu/m, a GaS-passivated device with a 0.5-/spl mu/m gate length has the maximum transconductance (g/sub m max/) of 347 mS/mm, which is about 40% higher than that of 240 mS/mm for a device without GaS passivation. We found that one of the causes of an increased g/sub m max/ is the decrease of sheet resistance on the recessed surface because GaS passivation has reduced the depletion layer. Meanwhile, the two-terminal gate-to-drain reverse breakdown voltage (BV/sub gd/) was reduced after GaS passivation. The BV/sub gd/ is independent of the recess length between gate and drain (L/sub gd/) for GaS-passivated devices, unlike that for devices without GaS passivation. According to our calculation of the BV/sub gd/ involving the effects of impact ionization and the interface state, the BV/sub gd/ becomes almost independent of the L/sub gd/, when the interface state density (N/sub int/) is below 1/spl times/10/sup 12/ cm/sup -2/. Then, the calculated surface potential at the recess region is less than 0 eV. This result suggests that GaS passivation can remarkably reduce the N/sub int/ at the recess region.     

Improved device performance and reliability in high /spl kappa/ HfTaTiO gate dielectric with TaN gate electrode

The device performance and reliability of higher-/spl kappa/ HfTaTiO gate dielectrics have been investigated in this letter. HfTaTiO dielectrics have been reported to have a high-/spl kappa/ value of 56 and acceptable barrier height relative to Si (1.0 eV). Through process optimization, an ultrathin equivalent oxide thickness (EOT) (/spl sim/9 /spl Aring/) has been achieved. HfTaTiO nMOSFET characteristics have been studied as well. The peak mobility of HfTaTiO is 50% higher than that of HfO/sub 2/ and its high field mobility is comparable to that of HfSiON with an intentionally grown SiO/sub 2/ interface, indicative of superior quality of the interface and bulk dielectric. In addition, HfTaTiO dielectric has a reduced stress-induced leakage current (SILC) and improved breakdown voltage compared to HfO/sub 2/ dielectric.     

Effect of low-temperature interphase charge transport at the Si/SiO2 interface on the photoresponse of silicon barrier structures

The effect of low-temperature electron charge redistribution at the Si/SiO₂ interface between the interphase states and the conduction band of an n-Si crystal on the temperature behavior of conductance, photovoltage, and photocurrent in Si barrier structures with edge surface electron channels was studied in the temperature range of 77–300 K. The dynamics of the channel-current response to the voltage changes in the dark and under illumination can be explained qualitatively by dispersive hopping transport of holes in SiO₂, which induces electron transfer to, and accumulation at, the Si surface near the barrier contact. The leveling off of the photovoltage at low temperatures and the nonmonotonic temperature dependence of the photocurrent are attributed to the nonmonotonically increasing, localized hole density at the Si/SiO₂ interface and the free electron density at the Si surface with decreasing temperature, which reflects changes in the valence of oxygen complexes.     

A High Schottky-Barrier of 1.1 eV Between Al and S-Passivated p-Type Si(100) Surface

We report a high Schottky-barrier between Al and S-passivated p-type Si(100) surface. Capacitance-voltage measurements indicate a barrier height of 1.1 eV, while activation-energy measurements suggest 0.94-0.97 eV. Possible reasons for the discrepancy are proposed. The barrier height of 1.1 eV suggests degenerate inversion on the p-type Si surface, and Fermi statistics is used to describe its electrostatics. Although fabricated like a Schottky diode, this Al/S-passivated p-type Si(100) device works like a p-n junction diode. Temperature-dependent current-voltage measurements reveal that S passivation reduces the reverse saturation current of Al/p-type Si(100) diodes by over six orders of magnitude     

Transformation of interface states in silicon-on-insulator structures under annealing in hydrogen atmosphere

Changes induced by annealing the spectrum of states on a Si/SiO₂ interface obtained by direct bonding and on a Si(substrate)/〈thermal SiO₂〉 interface in silicon-on-insulator (SOI) structures were investigated by charge-related deep-level transient spectroscopy. The structures were formed by bonding silicon wafers and slicing one of the wafers along a plane weakened by hydrogen implantation. The SOI structures were annealed at 430°C for 15 min in hydrogen, which corresponded to the conventional mode of passivation of the Si/SiO₂-interface states. The passivation of interface states by hydrogen was shown to take place for the Si/〈thermal SiO₂〉 interface, as a result of which the density of traps substantially decreased, and the continuous spectrum of states was replaced by a band of states in the energy range E _c=0.1–0.35 eV within the entire band. For the traps on the bonded Si/SiO₂ interface, the transformation of the centers occurs; namely, a shift of the energy-state band is observed from E _c=0.17–0.36 to 0.08–0.22 eV. The trapping cross section decreases by about an order of magnitude, and the density of traps observed increases slightly.     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

Optical and electrical properties of nanostructured metal-silicon-metal photodetectors

We report an experimental evaluation of the performance of silicon (Si) photodetectors incorporating one-dimensional (1-D) arrays of rectangular and triangular-shaped nanoscale structures within their active regions. A significant (/spl sim/2/spl times/) enhancement in photoresponse is achieved in these devices across the 400- to 900-nm spectral region due to the modification of optical absorption properties that results from structuring the Si surface on physical optics scales smaller than the wavelength, which both reduces the reflectivity and concentrates the optical field closer to the surface. Both patterned (triangular and rectangular lineshape) and planar Ni-Si back-to-back Schottky barrier metal-semiconductor-metal photodetectors on n-type (/spl sim/5/spl times/10/sup 14/ cm/sup -3/) bulk Si were studied. 1-D /spl sim/50-250-nm linewidth, /spl sim/1000-nm depth, grating structures were fabricated by a combination of interferometric lithography and dry etching. The nanoscale grating structures significantly modify the absorption, reflectance, and transmission characteristics of the semiconductor: air interface. These changes result in improved electrical response leading to increased external quantum efficiency (from /spl sim/44% for planar to /spl sim/81% for structured devices at /spl lambda/=700 nm). In addition, a faster time constant (/spl sim/1700 ps for planar to /spl sim/600 ps for structured at /spl lambda/=900 nm) is achieved by increasing the absorption near the surface where the carriers can be rapidly collected. Experimental quantum efficiency and photocurrents results are compared with a theoretical photocurrent model based on rigorous coupled-wave analysis of nanostructured gratings.     

Three-interface pseudo-MOSFET models for the characterization of SOI wafers with ultrathin film and BOX

The electrical characterization of unprocessed fully depleted silicon-on-insulator (SOI) layers relies on the pseudo-MOSFET (Ψ-MOSFET) technique. We propose three-interface models which are more appropriate for addressing the case of SOI wafers with ultrathin body and BOX (UTB²). The novel models for threshold voltage and subthreshold swing account for the channel-to-surface and channel-to-substrate coupling which are important effects, respectively, in ultrathin films and thin BOX. The influence of the density of traps at each of the three interfaces (free surface, channel/BOX and BOX/substrate) is discussed. The models are validated with experimental results from a range of SOI film thicknesses.     

Polyimide passivated AlGaN-GaN HFETs with 7.65 W/mm at 18 GHz

Current metal-organic chemical vapor deposition-grown AlGaN-GaN heterojunction field-effect transistor devices suffer from threading dislocations and surface states that form traps, degrading RF performance. A passivation scheme utilizing a polyimide film as the passivating layer was developed to reduce the number of surface states and minimize RF dispersion. Continuous-wave power measurements were taken at 18 GHz on two-finger 0.23-/spl mu/m devices with 2/spl times/75 /spl mu/m total gate width before and after passivation yielding an increase from 2.14 W/mm to 4.02 W/mm in power density, and 12.5% to 24.47% in power added efficiency. Additionally, a 2/spl times/25 /spl mu/m device yielded a peak power density of 7.65 W/mm at 18 GHz. This data suggests that polyimide can be an effective passivation film for reducing surface states.     

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.     

/sup 60/Co gamma irradiation effects on n-GaN Schottky diodes

The effect of /spl gamma/-ray exposure on the electrical characteristics of nickel/n-GaN Schottky barrier diodes has been investigated using current-voltage (I-V), capacitance-voltage (C-V), and deep-level transient spectroscopy (DLTS) measurements. The results indicate that /spl gamma/-irradiation induces an increase in the effective Schottky barrier height extracted from C-V measurements. Increasing radiation dose was found to degrade the reverse leakage current, whereas its effect on the forward I-V characteristics was negligible. Low temperature (/spl les/50) post-irradiation annealing after a cumulative irradiation dose of 21 Mrad(Si) was found to restore the reverse I-V characteristics to pre-irradiation levels without significantly affecting the radiation-induced changes in C-V and forward I-V characteristics. Three shallow radiation-induced defect centers with thermal activation energies of 88 104 and 144 meV were detected by DLTS with a combined production rate of 2.12 /spl times/ 10/sup -3/ cm/sup -1/. These centers are likely to be related to nitrogen-vacancies. The effect of high-energy radiation exposure on device characteristics is discussed taking into account possible contact inhomogeneities arising from dislocations and interfacial defects. The DLTS results indicate that GaN has an intrinsically low susceptibility to radiation-induced material degradation, yet the effects observed in the Schottky diode I-V and C-V characteristics indicate that the total-dose radiation hardness of GaN devices may be limited by susceptibility of the metal-GaN interface to radiation-induced damage.     

Kullback-Leibler approximation of spectral density functions

We introduce a Kullback-Leibler (1968) -type distance between spectral density functions of stationary stochastic processes and solve the problem of optimal approximation of a given spectral density /spl Psi/ by one that is consistent with prescribed second-order statistics. In general, such statistics are expressed as the state covariance of a linear filter driven by a stochastic process whose spectral density is sought. In this context, we show (i) that there is a unique spectral density /spl Phi/ which minimizes this Kullback-Leibler distance, (ii) that this optimal approximate is of the form /spl Psi//Q where the "correction term" Q is a rational spectral density function, and (iii) that the coefficients of Q can be obtained numerically by solving a suitable convex optimization problem. In the special case where /spl Psi/ = 1, the convex functional becomes quadratic and the solution is then specified by linear equations.     

Long-wavelength In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As large-area avalanche photodiodes and arrays

Large-area (500-/spl mu/m diameter) mesa-structure In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiodes (APDs) are reported. The dark current density was /spl sim/2.5/spl times/10/sup -2/ nA//spl mu/m/sup 2/ at 90% of breakdown; low surface leakage current density (/spl sim/4.2 pA//spl mu/m) was achieved with wet chemical etching and SiO/sub 2/ passivation. An 18 /spl times/ 18 APD array with uniform distributions of breakdown voltage, dark current, and multiplication gain has also been demonstrated. The APDs in the array achieved 3-dB bandwidth of /spl sim/8 GHz at low gain and a gain-bandwidth product of /spl sim/120 GHz.     

Impact of nitrogen incorporation on interface states in (1 0 0)Si/HfO2

The energy distribution of (1 0 0)Si/HfO₂ interface states and their passivation by hydrogen are studied for different levels of nitrogen incorporation using different technological methods. The results are compared to those of N-free samples. The nitrogen in the (1 0 0)Si/HfO₂ entity is found to increase the trap density in the upper part of the Si band gap and to hinder the passivation of traps in molecular hydrogen in this energy range. At the same time, the passivation of fast interface traps in the lower part of the band gap proceeds efficiently, provided the thickness of the grown Si₃N₄ interlayer is kept minimal. However, the lowest achievable interface trap density below midgap is set by the presence of slow N-related states, likely related to traps in the insulator.     

Improvement in NBTI reliability of Si-passivated Ge/high-k/metal-gate pFETs

State-of-the-art germanium-based p-channel FET devices are shown to have normal Negative Bias Temperature Instability (NBTI) behavior typically observed in Silicon-based pFETs. Furthermore, NBTI in Ge pFETs is reduced with respect to their Si counterparts. This improvement quantitatively corresponds to the reduction due to the tunneling barrier for holes formed by the Si passivation layer. A strong reduction in the permanent NBTI component is ascribed to a higher initial number of interface states.     

Effect of the surface and barrier defects on the AlGaN/GaN HEMT low-frequency noise performance

We report on the effect of Si/sub 3/N/sub 4/ passivation of the surface of AlGaN/GaN transistors on low-frequency noise performance. Low-frequency noise measurements were performed on the device before and after the passivation by a Si/sub 3/N/sub 4/ film. A lower level of the low-frequency noise was observed from the device after the passivation. The passivation layer improved high-frequency, large-signal device performance, but introduced parasitic leakage current from the gate. A lower level of flicker noise is explained by the fact that noise is mostly originated from the fluctuation of sheet charge and mobility in the ungated region of the device due to the defects on the surface and in the barrier of the unpassivated device. Passivation eliminates part of the defects and higher leakage current increases the number of electrons on the surface and in the vicinity of the barrier defects, lowering the contribution to the low-frequency noise according to Hooge's law.