A broadband linear-in-decibel variable gain amplifier with low gain error

A new circuit architecture for broadband digitally controlled variable gain amplifier (VGA) is introduced in this paper. The gain of the VGA is controlled precisely by using a resistor ladder attenuator and a closed-loop fine gain control block together. The bandwidth of the VGA is extended by applying a compensation technique in the fine gain control block. Implemented in 0.13-μm CMOS technology, the proposed VGA demonstrates a decibel-linear gain range of 24 dB (0–24 dB) with a gain step of 0.1 dB, a gain error <0.08 dB, a maximum input-referred third-order intercept point (IIP3) of 22.8 dBm, and a 3-dB bandwidth of 600 MHz.     

A low power high linearity baseband for a direct conversation CMMB tuner

An analog baseband circuit made in a 0.35-μm SiGe BiCMOS process is presented for China Multimedia Mobile Broadcasting (CMMB) direct conversion receivers. A high linearity 8th-order Chebyshev low pass filter (LPF) with accurate calibration system is used. Measurement results show that the filter provides 0.5-dB passband ripple, 4% bandwidth accuracy, and -35-dB attenuation at 6 MHz with a cutoff frequency of 4 MHz. The current steering type variable gain amplifier (VGA) achieves more than 40-dB gain range with excellent temperature compensation. This tuner baseband achieves an OIP3 of 25.5 dBm, dissipates 16.4 mA under a 2.8-V supply and occupies 1.1 mm2 of die size.     

A 0.8-3 GHz RF-VGA with 35 dB dynamic range in 0.13μm CMOS

正A wideband variable gain amplifier(VGA) implemented in 0.13μm CMOS technology is presented. To optimize noise performance,an active feedback amplifier with 15 dB fixed gain is put in the front,followed by modified Cherry-Hooper amplifiers in cascade providing variable gain,which adopt dual loop feedback for bandwidth extension.Negative capacitive neutralization and capacitive source degeneration are employed for Miller effect compensation and DC offset cancellation,respectively.Measurement results show that the proposed VGA achieves a 35 dB gain tuning range with an upper 3-dB bandwidth larger than 3 GHz and the input 1 dB compression point of-29 dBm at the lowest gain state,while the minimum noise figure is 9 dB at the highest gain state. The core VGA(without test buffer) consumes 32 mW from 1.2 V power supply and occupies 0.48 mm2 area.     

A CMOS VGA With DC Offset Cancellation for Direct-Conversion Receivers

A CMOS dB-linear variable gain amplifier (VGA) with a novel I/Q tuning loop for dc-offset cancellation is presented. The CMOS dB-linear VGA provides a variable gain of 60 dB while maintaining its 3-dB bandwidth greater than 2.5 MHz. A novel exponential circuit is proposed to obtain the dB-linear gain control characteristics. Nonideal effects on dB linearity are analyzed and the methods for improvement are suggested. A varying-bandwidth LPF is employed to achieve fast settling. The chip is fabricated in a 0.35- $mu{hbox {m}}$ CMOS technology and the measurement results demonstrate the good dB linearity of the proposed VGA and show that the tuning loop can effectively remove dc offset and suppress I/Q mismatch effects simultaneously.      

A 60-dB linear VGA with novel exponential gain approximation

A CMOS variable gain amplifier (VGA) that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved. The three-stage VGA with automatic gain control (AGC) and DC offset cancellation (DCOC) is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ± 1 dB. The 3-dB bandwidth is over 8 MHz at all gain settings. The measured input-referred third intercept point (IIP3) of the proposed VGA varies from -18.1 to 13.5 dBm, and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz. The dynamic range of the closed-loop AGC exceeds 56 dB, where the output signal-to-noise-and-distortion ratio (SNDR) reaches 20 dB. The whole circuit, occupying 0.3 mm2 of chip area, dissipates less than 3.7 mA from a 1.8-V supply.     

一种具有温度补偿的宽带CMOS可变增益放大器

设计实现了一个具有温度补偿的宽带CMOS可变增益放大器,该可变增益放大器的核心电路由三级基于改进型Cherry-Hooper结构的可变增益单元级联而成,并通过一种温度系数增强的且可编程的偏置电路和增益控制电路对可变增益放大器的增益进行温度补偿。采用中芯国际0.13μm CMOS工艺流片,测试结果表明可变增益放大器的可变增益范围为-13～27dB,经过温度补偿后,在相同增益控制电压下其增益在0～75°C温度范围内的变化范围不超过3dB。可变增益放大器的3dB带宽为0.8～3GHz,输入1dB压缩点为-50～-21dBm,在1.2V电压下,功耗为21.6mW。     

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ transimpedance gain, 20.4-GHz −3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10⁻¹² BER at 26 Gb/s for a 2¹⁵−1 PRBS input with a −7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.     

A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.     

一种dB线性数字控制可变增益放大器的设计

设计了一种dB线性增益的数字控制可变增益放大器。以二极管做负载的全差分输入共源极放大器为原型,通过同时同比例地改变输入输出晶体管尺寸比和偏置电流比来控制增益变化,使输入输出晶体管的电流密度保持一恒定值,提高了电路在低增益时的线性度。电路采用NEC 0.35μm CMOS标准工艺库进行设计。仿真结果表明,dB线性增益范围为-11.85dB到11.64dB,增益误差小于0.5dB。增益为-11.85dB时,其1-dB压缩点达到8.35dBm,-3dB增益带宽大于62MHz,并且随设定的增益值在62MHz和240MHz之间变化。     

CMOS宽带可变增益放大器

设计了一种CMOS宽带、低功耗可变增益放大器.在分析使用源极退化电阻的共源放大器高频特性基础上,通过加入频率补偿电容改变放大器的零极点分布,在不增加功耗的情况下扩展了带宽.分析了放大器在低增益下出现的增益尖峰现象并加以解决.使用跨导增强电路提高了放大器的线性度.两级可变增益放大器使用TSMC0.25μm CMOS工艺.仿真结果表明,放大器在3.3V电压下核心电路功耗为3.15mW,增益范围0～40dB;在负载为5pF电容时3dB带宽大于340MHz,输出三阶交调点高于3.5dBm.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

A 50-MHz CMOS variable gain amplifier for magnetic data storagesystems

A variable-gain amplifier (VGA) with a 35-dB range and 50-MHz bandwidth in 2-μm CMOS is described. The circuit occupies 0.8-mm² active area, dissipates 150 mW, and embodies a semilogarthic relation between gain and control voltage. Although developed for use in magnetic storage read channels, this general-purpose block may be used in a variety of applications     

A 95-dB linear low-power variable gain amplifier

An all-CMOS variable gain amplifier (VGA) that adopts a new approximated exponential equation is presented. The proposed VGA is characterized by a wide range of gain variation, temperature-independence gain characteristic, low-power consumption, small chip size, and controllable dynamic gain range. The two-stage VGA is fabricated in 0.18-/spl mu/m CMOS technology and shows the maximum gain variation of more than 95 dB and a 90-dB linear range with linearity error of less than /spl plusmn/ 1 dB. The range of gain variation can be controlled from 68 to 95 dB. The P1dB varies from - 48 to - 17 dBm, and the 3-dB bandwidth is from 32 MHz (at maximum gain of 43 dB) to 1.05 GHz (at minimum gain of - 52 dB). The VGA dissipates less than 3.6 mA from 1.8-V supply while occupying 0.4 mm/sup 2/ of chip area excluding bondpads.     

A low-power low-noise accurate linear-in-dB variable-gain amplifierwith 500-MHz bandwidth

A linear-in-dB variable-gain amplifier (VGA) using a pre-distortion circuit to generate the gain-control signal is fabricated in a BiCMOS process with f_T=20 GHz. The VGA comprises two cascaded stages of signal-summing VGA and has a variable-gain range of over 70 dB. It can operate at up to 500 MHz and dissipates 36 mW from a 3-V supply. A noise figure of below 5 dB and IIP3 of over -38 dBm at 43-dB gain were obtained. The VGA achieved a gain error of less than 2 dB over 70-dB gain range, and it occupies approximately 1 mm². The VGA is applicable to future code division multiple access (CDMA) receivers     

A 2.5-V 56-mW baseband chain in a multistandard TV tuner for mobile and multimedia applications

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm~2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.     

DC to 40-GHz broad-band amplifiers using AlGaAs/GaAs HBT's

In this paper, we report two types of broad-band amplifiers implemented with AlGaAs/GaAs HBT's. One is a Darlington feedback amplifier and the other is a transimpedance amplifier. In the former circuit, a dc gain of 9.5 dB and a -3-dB bandwidth of 40 GHz were achieved. In the latter circuit, a transimpedance gain of 50 dBΩ and a -3-dB bandwidth of 27 GHz were achieved. To our best knowledge, they are the highest speed in each circuit configuration     

An Improved-Linearity,Single-Stage Variable-Gain Amplifier Using Current Squarer for Wider Gain Range

A novel single-stage variable-gain amplifier (VGA) based on transconductance \(g_{m}\)-ratio amplifier is analyzed and designed with wider linear-in-dB gain range and improved linearity. The variable-gain amplifier proposed here consists of an exponential control block, a current squarer and an amplifier block with both input and load degeneration. With the help of current squarer which gets square function of the output current from exponential control block, the VGA achieves the maximum linear gain range in single stage. Current squarer is proposed, which is designed with compensation technique to minimize the second-order effect caused by carrier mobility reduction in short channel MOSFET. To avoid the poor linearity performance of the \(g_{{m}}\)-ratio amplifiers, the distortion is analyzed and the linearity is improved by applying input and load degenerating technique. At the same power consumption, the input 1 dB compression point can be improved by nearly 8.78 dB. Simulation results show that the VGA can provide a gain variation range of 64.09 dB (from \(-35.59\) to 28.5 dB) with a 3-dB bandwidth from 47 to 640 MHz. The circuit consumes the maximum power 3.5 mW from a 1.8-V supply.     

Broad-band GaAs monolithic equalizing amplifiers formultigigabit-per-second optical receivers

The authors discuss the development of ICs (integrated circuits) for a preamplifier, a gain-controllable amplifier, and main amplifiers with and without a three-way divider for multigigabit-per-second optical receivers using a single-ended parallel feedback circuit, two (inductor and capacitor) peaking techniques, and advanced GaAs process technology. An optical front-end circuit consisting of a GaAs preamplifier and an InGaAs p-i-n photodiode achieves a 3-dB bandwidth of 7 GHz and -12-dBm sensitivity at 10 Gb/s. Moreover, a gain-controllable amplifier obtains a maximum gain of 15 dB, a gain dynamic range of 25 dB, and a 3-dB bandwidth of 6.1 GHz by controlling the source bias of the common-source circuit. Gain, 3-dB bandwidth, and output power of the main amplifier with the three-way divider are 17.4 dB, 5.2 GHz, and 5 dBm, respectively. These ICs can be applied to optical receivers transmitting NRZ signals in excess of 7 Gb/s     

A broad-band amplifier using GaAs/GaAlAs heterojunction bipolartransistors

A compact wideband amplifier (or gain block) designed around a Darlington pair of GaAs/GaAlAs heterojunction bipolar transistors (HBTs) is discussed. This circuit has been fabricated by an ion-implanted process with a transistor f_t of 40 GHz. Two variants of the circuit gave either a 8.5-dB gain with a DC-to-5-GHz 3-dB bandwidth or a 13-dB gain with a DC-to-3-GHz bandwidth. These amplifiers gave 11.8- and 18.3-dBm output, respectively, at 1-dB gain compression     

用于超宽带接收机的高速低复杂度模拟自动增益控制环路

在射频接收机中,自动增益控制环路(AGC)根据接收信号幅度控制放大器增益,向后级模数转换器(ADC)提供恒定幅度的信号,以实现不同强度信号的正确接收。在超宽带(UWB)接收机中,极大的信号带宽给AGC的设计提出了挑战。本文提出了一个用于超宽带(UWB)接收机的模拟自动增益控制环路(AGC)。该AGC环路采用多级可变增益放大器(VGA)串联的放大器结构,通过峰值检测电路和模值运算电路检测输出复信号模值的峰值,和参考电位比较后反馈控制VGA的增益,从而得到恒定幅值的ADC的输入。整个电路结构简单,复杂度低。基于HJ0.18μmCMOS工艺的仿真结果表明,本文提出的AGC工作在500MHz带宽下,增益调节范围达40dB,三阶交调点为20dBm,能够满足UWB接收机的要求。