Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application

This paper is for process development of assembly technologies used to fabricate the 3-D silicon carrier system-in–package (SiP). The five assembly technologies are wafer thinning, thin flip chip attach on silicon carrier, ultra low loop wire bonding, glass cap fabrication and sealing, and silicon carrier stacking. The developed SiP has three silicon carriers with four flip chip and one wire bond die chip attached to them and the carrier is stacked one above the other to form the 3-D silicon carrier SiP. Eight-inch bumped wafer thinning down to less than 100 $mu{hbox {m}}$, lower flip chip interconnect height between the chip and the carrier down to 35 $mu{hbox {m}}$, 40–50- $mu{hbox {m}}$ low loop wire bonding on overhang by direct reverse wire bonding method using 1-mil-diameter Au wire are achieved. And investigation of three types of thin film metallization systems for wirebonding and investigation of two different methods in fabricating glass cap are also studied.      

Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages

This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.     

High-density 3-D packaging technology based on the sidewall interconnection method and its application for CCD micro-camera visual inspection system

High-density three-dimensional (3-D) packaging technology for a charge coupled device (CCD) micro-camera visual inspection system module has been developed by applying high-density interconnection stacked unit modules. The stacked unit modules have fine-pitch flip-chip interconnections within Cu-column-based solder bumps and high-aspect-ratio Cu sidewall footprints for vertical interconnections. Cu-column-based solder bump design and underfill encapsulation resin characteristics were optimized to reduce the strain in the bump so as to achieve fine-pitch flip-chip interconnection with high-reliability. High-aspect-ratio Cu sidewall footprints were realized by the Cu-filled stacked vias at the edge of the substrate. High-precision distribution of sidewall footprints was achieved by laminating the multiple stacked unit substrates simultaneously. The fabricated high-density 3-D packaging module has operated satisfactorily as the CCD imaging data transmission circuit. The technology was confirmed to be effective for incorporating many large scale integrated (LSI) devices of different sizes at far higher packaging density than it is possible to attain using conventional technology. This paper describes the high-density 3-D packaging technology which enables all of the CCD imaging data transmission circuit devices to be packaged into the restricted space of the CCD micro-camera visual inspection system interior.     

Design, Fabrication, and Characterization of Novel Vertical Coaxial Transitions for Flip-Chip Interconnects

In this paper, a novel transition design using vertical “coaxial transition” for coplanar waveguide (CPW-to-CPW) flip-chip interconnect is proposed and presented for the first time. The signal continuity is greatly improved since the coaxial-type transition provides more return current paths compared to the conventional transition in the flip-chip structure. The proposed coaxial transition structure shows a real coaxial property from the 3-D electromagnetic wave simulation results. The design rules for the coaxial transition are presented in detail with the key parameters of the coaxial transition structure discussed. For demonstration, the back-to-back flip-chip interconnect structures with the vertical coaxial transitions have been successfully fabricated and characterized. The demonstrated interconnect structure using the coaxial transition exhibits the return loss below 25 dB and the insertion loss within 0.4 dB from dc to 40 GHz. Furthermore, the measurement and simulation results show good agreement. The novel coaxial transition demonstrates excellent interconnect performance for flip-chip interconnects and shows great potential for flip-chip packaging applications at millimeter waves.      

Characterization of flip-chip interconnects up to millimeter-wave frequencies based on a nondestructive in situ approach

In this paper, the performance of flip-chip interconnects at frequencies up to 40 GHz is presented based on a nondestructive in situ measurement approach. The method unfolds the raw flip-chip interconnect excluding any launch structures in concomitance of a mounted silicon chip. The results are compared with a commonly used two-port through measurement technique of coplanar wave (CPW)-to-CPW transitions without involvement of a silicon chip. Finally, the attempt has been made to extract the electrical performance from a directly probed flip-chip interconnect for the first time.     

Reliability of a Silicon Stacked Module for 3-D SiP Microsystem

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.     

Passive Immersion Cooling of 3-D Stacked Dies

Three-dimensional die stacking increases integrated circuit (IC) density, providing increased capabilities and improved electrical performance on a smaller printed circuit board (PCB) footprint area. However, these advantages come at the expense of higher volumetric heat generation rates and decreased thermal and mechanical access to the die areas. Passive immersion cooling, allowing for buoyancy-driven fluid flow between stacked dies, can provide high heat transfer coefficients directly on the die surfaces, can easily accommodate a wide variety of interconnect schemes, and is scalable to any number of dies. A methodology for the optimization of immersion cooled 3-D stacked dies is presented, including the effects of confinement on natural convection and channel boiling. Optimum die spacings for both single and two phase cooling with saturated FC-72 are found to be on the order of half a millimeter for typical microelectronics geometries and to yield heat densities of 10-50 W/cm³ in natural convection and 100-500 W/cm³ in channel boiling.     

3-D packaging methodologies for microsystems

Issues associated with the packaging of microsystems in plastic and three-dimensional (3-D) body styles are discussed. The integration of a microsystem incorporating a micromachined silicon membrane pump, into a 3-D plastic encapsulated vertical multichip module package (MCM-V) is described. Finite element techniques are used to analyze the encapsulation stress in the structure of the package. Cracks develop in the chip carrier due to thermomechanical stress. Based on the results of a finite element design study, the structures of the chip carriers are modified to reduce their risk of cracking. Alternative low stress 3-D packaging methodologies based on chip on board and plastic leadless chip carriers are discussed.     

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

The authors report the first demonstration of integrating wafer stacking via Cu bonding with strained-Si/low-k 65-nm CMOS technology. Sets of 330 mm wafers with active devices such as 65-nm MOSFETs and 4-MB SRAMs were bonded face-to-face using copper pads with size ranging between 5 /spl mu/m/spl times/5 /spl mu/m and 6 /spl mu/m/spl times/40 /spl mu/m. The top wafers were thinned to different thicknesses in the range 5 to 28 /spl mu/m. Through-silicon-vias (TSVs) and backside metallization were used to enable electrical testing of both wafers in the Cu-stacked configuration. We tested individual transistors in the thinned silicon of bonded wafer pairs where the thinned silicon thickness ranged from 14 to 19 /spl mu/m. All results showed that both n- and p-channel transistors preserved their electrical characteristics after Cu bonding, thinning, and TSV integration. We also demonstrated the functionality of stacked 65-nm 4-MB SRAMs by independently testing the cells in both the thinned wafer and the bottom wafer. For the SRAM, we tested a wider thinned wafer thickness range from 5 to 28 /spl mu/m. On all tested samples, we did not find any impact to the electrical performance of the arrays resulting from the three-dimensional (3-D) integration process. The stacked SRAM is an experimental demonstration of the use of 3-D integration to effectively double transistor packing density for the same planar footprint. The results presented in this letter enable further exploratory work in high-performance 3-D logic, which takes advantage of the improved interconnect delays offered by this Cu-bonding stacking scheme integrated with modern CMOS processes.     

Three-dimensional flip-chip on flex packaging for power electronicsapplications

We have extended the concept of flip-chip technology, which is widely used in IC packaging, to the packaging of three-dimensional (3-D) integrated power electronics modules (IPEMs). We call this new approach flip-chip on flex IPEM (FCOF-IPEM), because the power devices are flip-chip bonded to a flexible substrate with control circuits. We have developed a novel triple-stacked solder bump metallurgy for improved and reliable device interconnections. In this multilayer structure, we have carefully selected packaging materials that distribute the thermo-mechanical stresses caused by mismatching coefficients of thermal expansion (CTEs) among silicon chips and substrates. We have demonstrated the feasibility of this packaging approach by constructing modules with two insulated gate bipolar transistors (IGBTs), two diodes, and a simple gate driver circuit. Fabricated FCOF-IPEMs have been successfully tested at power levels up to 10 kW. This paper presents the materials and reliability issues in the package design along with electrical, mechanical, and thermal test results for a packaged IPEM     

Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication

This paper provides a detailed overview of silicon carrier-based packaging for 3-D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a three-step approach has been developed and characterized which controls via depth, sidewall profile, and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing, and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.      

Local clustering 3-D stacked CMOS technology for interconnect loading reduction

A three-dimensional (3-D) stacked CMOS technology is developed to closely pack devices in a number of standard cells to form local clusters. Based on the 3-D stacked CMOS technology, an analysis to extend the technology to implement standard cell-based integrated circuits is performed. It is found that the 3-D stacked CMOS technology can reduce the size of an overall IC by 50% with significant reduction in interconnect delay. A thermal analysis is also performed. It was found that the rise in temperature in 3-D ICs could be lower than that of traditional planar ICs under the condition of same propagation delay since the required power supply voltage of 3-D ICs to achieve the same performance is lower.     

Design optimization of one-turn helix: a novel compliant off-chip interconnect

As the rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great potential for next-generation packaging. One-turn helix (OTH) interconnect, a compliant chip-to-next level substrate or off-chip interconnect, is proposed in this work, and this interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The interconnect has high mechanical compliance in the three orthogonal directions, and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of the helix interconnect is similar to the standard IC fabrication, and the wafer-level packaging makes it cost effective. In this paper, we report the fabrication of an area array of helix interconnects on a silicon wafer. Also, we have studied the effect of interconnect geometry parameters on its mechanical compliance and electrical parasitics. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH interconnect. An optimization technique using response surface methodology has been applied to select the optimal structure parameters. The optimal compliant OTH interconnect will have a total standoff height of about 100 /spl mu/m, a radius of about 35 /spl mu/m and a cross section area of about 430 /spl mu/m/sup 2/.     

Signal Integrity Flow for System-in-Package and Package-on-Package Devices

As data rates required for systems in package (SiPs) increase and their complexity increases, signal integrity issues become increasingly difficult to address. The design flow of the SiP should therefore take into account these issues from the beginning. A design flow aimed at designing the SiP tracks is presented; its suitability for the design of packages comprising multiple stacked memories is verified through a design example. The proposed flow for signal integrity can be integrated easily within the complete design of the SiP.      

Chip-scale packaging of power devices and its application inintegrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D²BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D²BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V_CE(sat) and on-resistance of the D²BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D²BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported     

A flip-chip packaged coplanar 94 GHz amplifier module with efficient suppression of parasitic substrate effects

A flip-chip mounted W-band amplifier module with more than 15 dB gain between 82 and 105 GHz has been developed, based on a 0.15 /spl mu/m GaAs PHEMT technology. To predict the influence of the flip-chip transition, an equivalent circuit model of the flip-chip interconnects was developed. Lossy silicon (n-Si) flip-chip carriers were used to successfully minimize parasitic substrate modes and feed back effects. The flip-chip assembled coplanar 94 GHz amplifier MMIC was packaged in a WR-10 waveguide mount, using CPW-to-waveguide transitions realized on quartz substrates.     

用2.5D TSV实现多处理器SiP功能

本项目由Open-Silicon,GLOBALFOUNDRI ES和Amkor三家公司合作完成。两颗28nm的ARM处理器芯片,通过2.5D硅转接板实现集成。芯片的高性能集成通常由晶体管制程提高来实现,应用2.5D技术的Si P正成为传统芯片系统集成的有效替代。Open-Silicon负责芯片和硅转接板的设计,重点在于性能优化和成本降低。GLOBALFOUNDRI ES采用28nm超低能耗芯片工艺制造处理器芯片,而用65nm技术制造2.5D硅转接板。包括功耗优化和功能界面有效管理等概念得到验证。硅基板的高密度布线提供大量平行I/O,以实现高性能存储,并保持较低功耗。所开发的EDA设计参考流程可以用于优化2.5D设计。本文展示了如何将大颗芯片重新设计成较小的几颗芯片,通过2.5D硅转接板实现Si P系统集成,以降低成本,提高良率,增加设计灵活性和重复使用性,并减少开发风险。     

Design of a 3-D fully depleted SOI computational RAM

We introduce a three-dimensional (3-D) processor-in-memory integrated circuit design that provides progressively increasing processing power as the number of stacked dies increases, while incurring no extra design effort or mask sets. Innovative techniques for processor/memory redundancy and fast global bus evaluation are described. The architecture can be augmented with a nearest-neighbor physical 3-D communications network that can substantially reduce interconnect lengths and relieve routing congestion. The test chip, with 128 Kb of memory and 512 processing elements (PEs) on two fully depleted silicon-on-insulator (SOI) dies, can achieve a peak of 170 billion-bit-operations per second at 400 MHz.     

Substrate interconnect technologies for 3-D MEMS packaging

We report the development of 3-dimensional silicon substrate interconnect technologies, specifically for reducing the package size of a MOSFET relay. The ability to interconnect multiple chips at different elevations on a single substrate can significantly improve device performance and size. We present the process development of through-hole interconnects fabricated using deep reactive ion etching (DRIE), with an emphasis on achieving positively tapered, smooth sidewalls to ease deposition of a seed layer for subsequent Cu electroplating. Gray-scale technology is integrated on the same substrate to provide smooth inclined surfaces between multiple vertical levels (>100 μm apart), enabling interconnection between the two levels via simple metal evaporation and lithography. The developments discussed for each technique may be used together or independently to address future packaging and integration needs.