Ab␣Initio Study of Aluminium Impurity and Interstitial-Substitutional Complexes in Ge Using a Hybrid Functional (HSE)

The results of an ab?initio modelling of aluminium substitutional impurity (\({\hbox {Al}}_{\rm Ge}\)), aluminium interstitial in Ge [\({\hbox {I}}_{\rm Al}\) for the tetrahedral (T) and hexagonal (H) configurations] and aluminium interstitial-substitutional pairs in Ge (\({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\)) are presented. For all calculations, the hybrid functional of Heyd, Scuseria, and Ernzerhof in the framework of density functional theory was used. Defects formation energies, charge state transition levels and minimum energy configurations of the \({\hbox {Al}}_{\rm Ge}\), \({\hbox {I}}_{\rm Al}\) and \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) were obtained for ?2, ?1, 0, \(+\)1 and \(+\)2 charge states. The calculated formation energy shows that for the neutral charge state, the \({\hbox {I}}_{\rm Al}\) is energetically more favourable in the T than the H configuration. The \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) forms with formation energies of ?2.37 eV and ?2.32 eV, when the interstitial atom is at the T and H sites, respectively. The \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) is energetically more favourable when the interstitial atom is at the T site with a binding energy of 0.8 eV. The \({\hbox {I}}_{\rm Al}\) in the T configuration, induced a deep donor (\(+\)2/\(+1\)) level at \(E_{\mathrm {V}}+0.23\) eV and the \({\hbox {Al}}_{\rm Ge}\) induced a single acceptor level (0/?1) at \(E_{\mathrm {V}}+0.14\) eV in the band gap of Ge. The \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) induced double-donor levels are at \(E_{\rm V}+0.06\) and \(E_{\rm V}+0.12\) eV, when the interstitial atom is at the T and H sites, respectively. The \({\hbox {I}}_{\rm Al}\) and \({\hbox {I}}_{\rm Al}{\hbox {Al}}_{\rm Ge}\) exhibit properties of charge state-controlled metastability.     

The Influence of Current Direction on the Cu-Ni Cross-Interaction in Cu/Sn/Ni Diffusion Couples

The influence of current direction on the Cu-Ni cross-interaction in the Cu/Sn/Ni joint configuration was investigated in this study. During current stressing, an electric current towards or away from the Ni-side of Cu/Sn/Ni was imposed at 150°C. It was observed that the (Cu,Ni)₆Sn₅ ternary compound was the dominant reaction product at both interfaces, and its growth at the Ni-side strongly depended upon the direction and magnitude of the electron flow. When the electron flow was towards the Ni-side, more Cu was found to be driven to the Ni-side, resulting in an increase in the thickness of (Cu,Ni)₆Sn₅. This is due to the chemical-potential-induced Cu flux (\( J_{\rm{chem}}^{\rm{Cu}} \)) that was enhanced by the electromigration (\( J_{\rm{em}}^{\rm{Cu}} \)). In the case of electron flow away from the Ni-side, the supply of Cu to the Ni-side was retarded due to the fact that \( J_{\rm{em}}^{\rm{Cu}} \) was in the opposite direction to \( J_{\rm{chem}}^{\rm{Cu}} . \) The results of this study revealed that the Ni-side (Cu,Ni)₆Sn₅ thickness remained almost unchanged under current stressing of 10⁴ A/cm² at 150°C, which suggests the inward Cu flux is approximately equal to the outward flux, i.e., \( J_{\rm{chem}}^{\rm{Cu}} \approx J_{\rm{em}}^{\rm{Cu}} . \)     

Application of photonic crystal ring resonator nonlinear response for full-optical tunable add–drop filtering

In this paper, we investigate the application of Kerr-like nonlinear photonic crystal (PhC) ring resonator (PCRR) for realizing a tunable full-optical add–drop filter. We used silicon (Si) nano-crystal as the nonlinear material in pillar-based square lattice of a 2DPhC. The nonlinear section of PCRR is studied under three different scenarios: (1) first only the inner rods of PCRR are made of nonlinear materials, (2) only outer rods of PCRR have nonlinear response, and (3) both of inner and outer rods are made of nonlinear material. The simulation results indicate that optical power required to switch the state of PCRR from turn-on to turn-off, for the nonlinearity applied to inner PCRR, is at least \(2000\, \hbox {mW}{/}\upmu \hbox {m}^{2}\) and, for the nonlinearity applied to outer PCRR, is at least \(3000\, \hbox {mW}{/}\upmu \hbox {m}^{2}\) which corresponds to refractive index change of \(\Delta n_\mathrm{NL }= 0.085\) and \(\Delta n_\mathrm{NL }= 0.15\), respectively. For nonlinear tuning of add–drop filter, the minimum power required to 1 nm redshift the center operating wavelength \((\lambda _{0} = 1550\, \hbox {nm})\) for the inner PCRR scenario is \(125\, \hbox {mW}{/}\upmu \hbox {m}^{2}\) (refractive index change of \(\Delta n_\mathrm{NL}= 0.005)\). Maximum allowed refractive index change for inner and outer scenarios before switch goes to saturation is \(\Delta n_\mathrm{NL }= 0.04\) (maximum tune-ability 8 nm) and \(\Delta n_\mathrm{NL }= 0.012\) (maximum tune-ability of 24 nm), respectively. Performance of add–drop filter is replicated by means of finite-difference time-domain method, and simulations displayed an ultra-compact size device with ultra-fast tune-ability speed.     

Fabrication of a <Emphasis Type="Italic">p</Emphasis>–<Emphasis Type="Italic">n</Emphasis> Heterojunction Using Topological Insulator Bi<Subscript>2</Subscript>Te<Subscript>3</Subscript>–Si and Its Annealing Response

A junction device has been fabricated by growing p-type Bi₂Te₃ topological insulator (TI) film on an n-type silicon (Si) substrate using a thermal evaporation technique. Annealing using different temperatures and durations was employed to improve the quality of the film, as confirmed by microstructural study using x-ray diffraction (XRD) analysis and atomic force microscopy (AFM). The p–n diode characteristics of the junction devices were studied, and the effect of annealing investigated. An improved diode characteristic with good rectification ratio (RR) was observed for devices annealed for longer duration. Reduction in the leakage or reverse saturation current (\( I_{\rm{R}} \)) was observed with increase in the annealing temperature. The forward-bias current (\( I_{\rm{F}} \)) dropped in devices annealed above 400°C. The best results were observed for the sample device annealed at 450°C for 3 h, showing figure of merit (FOM) of 0.621 with RR ≈ 504 and \( I_{\rm{R}} \) = 0.25 μA. In terms of ideality factor, the sample device annealed at 550°C for 2 h was found to be the best with \( n \) = 6.5, RR ≈ 52.4, \( I_{\rm{R}} \) = 0.61 μA, and FOM = 0.358. The majority-carrier density \( \left( {N_{\rm{A}} } \right) \) in the p-Bi₂Te₃ film of the heterojunction was found to be on the order of 10⁹/cm³ to 10¹¹/cm³, quite close to its intrinsic carrier concentration. These results are significant for fundamental understanding of device applications of TI materials as well as future applications in solar cells.     

A 3.1–10.6 GHz UWB LNA Based on Self Cascode Technique for Improved Bandwidth and High Gain

In this work, we present a self cascode based ultra-wide band (UWB) low noise amplifier (LNA) with improved bandwidth and gain for 3.1–10.6 GHz wireless applications. The self cascode (SC) or split-length compensation technique is employed to improve the bandwidth and gain of the proposed LNA. The improvement in the bandwidth of SC based structure is around 1.22 GHz as compared to simple one. The significant enhancement in the characteristics of the introduced circuit is found without extra passive components. The SC based CS–CG structure in the proposed LNA uses the same DC current for operating first stage transistors. In the designed UWB LNA, a common source (CS) stage is used in the second stage to enhance the overall gain in the high frequency regime. With a standard 90 nm CMOS technology, the presented UWB LNA results in a gain \(\hbox {S}_{21}\) of \(20.10 \pm 1.65\,\hbox {dB}\) across the 3.1–10.6 GHz frequency range, and dissipating 11.52 mW power from a 1 V supply voltage. However, input reflection, \(\hbox {S}_{11}\), lies below \(-\,10\) dB from 4.9–9.1 GHz frequency. Moreover, the output reflection (\(\hbox {S}_{22}\)) and reverse isolation (\(\hbox {S}_{12}\)), is below \(-\,10\) and \(-\,48\) dB, respectively for the ultra-wide band region. Apart from this, the minimum noise figure (\(\hbox {NF}_{min}\)) value of the proposed UWB LNA exists in the range of 2.1–3 dB for 3.1–10.6 GHz frequency range with a a small variation of \(\pm \,0.45\,\hbox {dB}\) in its \(\hbox {NF}_{min}\) characteristics. Linearity of the designed LNA is analysed in terms of third order input intercept point (IIP3) whose value is \(-\,4.22\) dBm, when a two tone signal is applied at 6 GHz with a spacing of 10 MHz. The other important benefits of the proposed circuit are its group-delay variation and gain variation of \(\pm \,115\,\hbox {ps}\) and \(\pm \,1.65\,\hbox {dB}\), respectively.     

A Low-Voltage Fully Differential Pure Current Mode Current Operational Amplifier

In this paper a novel high-frequency fully differential pure current mode current operational amplifier (COA) is proposed that is, to the authors’ knowledge, the first pure MOSFET Current Mode Logic (MCML) COA in the world, so far. Doing fully current mode signal processing and avoiding high impedance nodes in the signal path grant the proposed COA such outstanding properties as high current gain, broad bandwidth, and low voltage and low-power consumption. The principle operation of the block is discussed and its outstanding properties are verified by HSPICE simulations using TSMC \(0.18\,\upmu \hbox {m}\) CMOS technology parameters. Pre-layout and Post-layout both plus Monte Carlo simulations are performed under supply voltages of \(\pm 0.75\,\hbox {V}\) to investigate its robust performance at the presence of fabrication non-idealities. The pre-layout plus Monte Carlo results are as; 93 dB current gain, \(8.2\,\hbox {MHz}\,\, f_{-3\,\text {dB}}, 89^{\circ }\) phase margin, 137 dB CMRR, 13 \(\Omega \) input impedance, \(89\,\hbox {M}\Omega \) output impedance and 1.37 mW consumed power. Also post-layout plus Monte Carlo simulation results (that are generally believed to be as reliable and practical as are measuring ones) are extracted that favorably show(in abovementioned order of pre-layout) 88 dB current gain, \(6.9\,\hbox {MHz} f_{-3\text {db}} , 131^{\circ }\) phase margin and 96 dB CMRR, \(22\,\Omega \) input impedance, \(33\,\hbox {M}\Omega \) output impedance and only 1.43 mW consumed power. These results altogether prove both excellent quality and well resistance of the proposed COA against technology and fabrication non-idealities.     

Electrochemical,Structural and Magnetic Analysis of Electrodeposited CoCu/Cu Multilayers: Influence of Cu Layer Deposition Potential

The electrochemical, structural and magnetic properties of CoCu/Cu multilayers electrodeposited at different cathode potentials were investigated from a single bath. The Cu layer deposition potentials were selected as \(-\,0.3,\,\hbox {V}\) \(-\,0.4\,\,\hbox {V}\), and \(-\,0.5\,\hbox {V}\) with respect to saturated calomel electrode (SCE) while the Co layer deposition potential was constant at \(-\,1.5\,\hbox {V}\) versus SCE. For the electrochemical analysis, the current-time transients were obtained. The amount of noble non-magnetic (Cu) metal materials decreased with the increase of deposition potentials due to anomalous codeposition. Further, current-time transient curves for the Co layer deposition and capacitance were calculated. In the structural analysis, the multilayers were found to be polycrystalline with both Co and Cu layers adopting the face-centered cubic structure. The (111) peak shifts towards higher angle with the increase of the deposition potentials. Also, the lattice parameters of the multilayers decrease from 0.3669 nm to 0.3610 nm with the increase of the deposition potentials from \(-\,0.3\,\hbox {V}\) to \(-\,0.5\,\hbox {V}\), which corresponds to the bulk values of Cu and Co, respectively. The electrochemical and structural results demonstrate that the amount of Co atoms increased and the Cu atoms decreased in the layers with the increase of deposition potentials due to anomalous codeposition. For magnetic measurements, the saturation magnetizations, \(M_s\) obtained from the magnetic curves of the multilayers were obtained as 212 kA/m, 276 kA/m, and 366 kA/m with \(-\,0.3\,\hbox {V}\), \(-\,0.4\,\hbox {V}\), and \(-\,0.5\,\hbox {V}\) versus SCE, respectively. It is seen that the \(M_s\) values increased with the increase of the deposition potentials confirming the increase of the Co atoms and decrease of the Cu amount. The results of electrochemical and structural analysis show that the deposition potentials of non-magnetic layers plays important role on the amount of magnetic and non-magnetic materials in the layers and thus on the magnetic properties of the multilayers.     

A Reduced-sp-$$\hbox {D3L}_{\mathrm{sum}}$$ Adder-Based High Frequency $$4\times 4$$4×4 Bit Multiplier Using Dadda Algorithm

A low-power, high-speed \(4\times 4\) multiplier using Dadda algorithm is proposed. The full adder blocks used in this multiplier have been designed using reduced-split precharge-data driven dynamic sum logic. Flip flops used in the pipeline registers have been designed to increase input signal noise margin, resulting in the minimization of output signal glitches. The multiplier circuit is implemented in 1P-9M Low-K UMC 90nm CMOS process technology. Post-layout simulations are carried out using Cadence Virtuoso. The proposed multiplier operates at a clock frequency of 3.5 GHz, with an average dynamic power consumption of 1.096 mW at a temperature of \(27\,^{\circ }\hbox {C}\) and 1 V supply voltage and occupies a chip area of \(76\,\upmu \hbox {m}\times 102\,\upmu \hbox {m}\).     

Study on the Effect of Mn,Zn, and Sb on Undercooling Behavior of Sn-Ag-Cu Alloys Using Differential Thermal Analysis

Differential thermal analysis (DTA) has been conducted on directionally solidified near-eutectic Sn-3.0 wt.%Ag-0.5 wt.%Cu (SAC), SAC \(+\) 0.2 wt.%Sb, SAC \(+\) 0.2 wt.%Mn, and SAC \(+\) 0.2 wt.%Zn. Laser ablation inductively coupled plasma mass spectroscopy was used to study element partitioning behavior and estimate DTA sample compositions. Mn and Zn additives reduced the undercooling of SAC from 20.4\(^\circ \hbox {C}\) to \(4.9^\circ \hbox {C}\) and \(2^\circ \hbox {C}\), respectively. Measurements were performed at cooling rate of \(10^\circ \hbox {C}\) per minute. After introducing 200 ppm \(\hbox {O}_2\) into the DTA, this undercooling reduction ceased for SAC \(+\) Mn but persisted for SAC \(+\) Zn.     

5.18–7.42 GHz LC-VCO in subthreshold regime with low power low phase noise and immunity to PVT variations in 130 nm CMOS technology

In this paper, we propose an LC-VCO using automatic amplitude control and filtering technique to eliminate frequency noise around 2\(\omega _0\). The LC-VCO is designed with TSMC 130 nm CMOS RF technology, and biased in subthreshold regime in order to get more negative transconductance to overcome the losses in the LC-Tank and achieve less power consumption. The designed VCO operates at 5.17 GHz and can be tuned from 5.17 to 7.398 GHz, which is corresponding to 35.5% tuning range. The VCO consumes through it 495–440.5 \(\upmu\)W from 400 mV dc supply. This VCO achieves a phase noise of \(-\,122.3\) and \(-\,111.7\) dBc/Hz at 1 MHz offset from 5.17 and 7.39 GHz carrier, respectively. The calculated Figure-of-merits (FoM) at 1 MHz offset from 5.17 and 7.39 GHz is \(-\,199.7\) and \(-\,192.4\) dBc/Hz, respectively. And it is under \(-\,190.5\) dBc/Hz through all the tuning range. The FoM\(_T\) at 1 MHz offset from 5.17 GHz carrier is \(-\,210.6\) dBc/Hz. The proposed design was simulated for three different temperatures (\(-\,55\), 27, \(125\,^{\circ }\hbox {C}\)), and three supply voltages (0.45, 0.4, 0.35 V), it was concluded that the designed LC-VCO presents high immunity to PVT variations, and can be used for multi-standard wireless LAN communication protocols 802.11a/b/g.     

Correction to: A subthreshold low-power CMOS LC-VCO with high immunity to PVT variations

This paper presents a capacitor-free low dropout (LDO) linear regulator based on a dual loop topology. The regulator utilizes two feedback loops to satisfy the challenges of hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes. The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0–100 pF capacitive load. The design has been taped out in a \(0.18\,\upmu \hbox {m}\) CMOS process. The proposed regulator has a low component count, area of \(0.012\, \hbox {mm}^2\) and is suitable for system-on-chip integration. It regulates the output voltage at 0.9 V from a 1.0–1.4 V supply. The measured results for a current step load from 250 to 500 \(\upmu \hbox {A}\) with a rise and fall time of \(1.5\,\upmu \hbox {s}\) are an overshoot of 26 mV and undershoot of 26 mV with a settling time of \(3.5\,\upmu \hbox {s}\) when \({C_L}\) between 0 and 100 pF. The proposed LDO regulator consumes a quiescent current of only \(10.5\,\upmu \hbox {A}\). The design is suitable for application with a current step edge time of 1 ns while maintaining \(\Delta V_{out}\) of 64 mV.     

A 0.36 μW/channel recorder for external ambulatory ECG recorders

There is an increasing demand for long-term ECG monitoring applications which are very low power, small size and capable of wireless data transmission. This paper presents an analog front-end and also modulator for long-term ECG recording purpose. The fully integrated system features three independent channels and a modulator. The analog front-end includes a voltage-to-time conversion and a tunable modulator to achieve a very low power consumption for wireless transmission of the data without analog to digital converter. The proposed system is designed and simulated in a \(0.18\,\upmu \hbox {m}\) CMOS technology and occupies only \(0.245\,\mathrm{mm}^{2}\). It can record ECG signal with 9.2-bit resolution while consuming only \(0.36\,\upmu {\mathrm{W}}\) per channel from a 0.9 V supply. Also, it can transmit data consuming just \(0.72\,{\upmu }\mathrm{W}\) per channel from a 0.9 V supply. The input referred noise of the readout channel is \(2.01\,\upmu {\mathrm{V}}_{{{\rm rms}}}\).     

Ultra-Fast Current Mode Sense Amplifier for Small $$I_{\mathrm{CELL}}$$ SRAM in FinFET with Improved Offset Tolerance

In this paper, a novel, high-performance and robust sense amplifier (SA) design is presented for small \(I_\mathrm{CELLl}\) SRAM, using fin-shaped field effect transistors (FinFET) in 22-nm technology. The technique offers data-line-isolated current sensing approach. Compared with the conventional CSA (CCSA) and hybrid SA (HSA), the proposed current feed-SA (CF-SA) demonstrates 2.15\(\times \) and 3.02\(\times \) higher differential current, respectively, for \({V}_{\mathrm{DD}}\) of 0.6 V. Our results indicate that even at the worst corner, CF-SA can provide 2.23\(\times \) and 1.7\(\times \) higher data-line differential voltage compared with CCSA and HSA, respectively. Further, 66.89 and 31.47 % reductions in the cell access time are achieved compared to the CCSA and HSA, respectively, under similar \(I_\mathrm{CELLl}\) and bit-line and data-line capacitance. Statistical simulations have proved that the CF-SA provides high read yield with 32.39 and 22.24 % less \(\upsigma _{\mathrm{Delay}}\). It also offers a much better read effectiveness and robustness against the data-line capacitance as well as \({V}_{\mathrm{DD}}\) variation. Furthermore, the CF-SA is able to tolerate a large offset of the input devices, up to 80 mV at \({V}_{\mathrm{DD}}=0.6\hbox {V}\).     

Study on Time Domain Characteristics of Memristive RLC Series Circuits

The notion of memristive system was first proposed in 2009. This concept of memory element has been extended from memristors \((\hbox {R}_{\mathrm{M}})\) to memcapacitors \((\hbox {C}_{\mathrm{M}})\) and meminductors \((\hbox {L}_{\mathrm{M}})\). Currently, the above elements are not available as off-the-shelf components. Therefore, based on the realization of a light-dependent resistor (LDR), memristor analog model, memcapacitor and meminductor analog circuit models based on \(\hbox {R}_{\mathrm{M}}-\hbox {C}_{\mathrm{M}}\) and \(\hbox {R}_{\mathrm{M}}-\hbox {L}_{\mathrm{M}}\) converters are first introduced. Then, instead of the traditional resistor, capacitor, and inductor, memristor-, memcapacitor-, and meminductor-equivalent circuits are used to determine the time domain characteristics of the RLC-mode circuits with mem-elements. These circuits are discussed in detail, and in particular, the phenomena caused by the memory characteristics of the mem-elements are studied. This research provides an important reference for further research into mem-element applications in circuit theory.     

Design and analysis of a feedback time difference amplifier with linear and programmable gain

This paper proposes a feedback time difference amplifier (FTDA) that achieves linear, controllable gain and changeable input range for different time difference gains. The proposed FTDA consists of two identical feedback output generators. The feedback output generator achieves a linear input–output transfer characteristic by employing two p-type keepers for time gain feedback control. Its validity was demonstrated using \({0.13}\, {\upmu \hbox {m}}\) SiGe BiCMOS process. The power consumption is \(91.54 \,{\upmu \hbox {W}}\) for the highest gain with input signals at \({2}\,\hbox {MHz}\). The gain can be controlled from 25.06 to \(734.9\,{\hbox {s/s}}\) within \(40 \,\hbox {ps}\) input time interval.     

Lower bounds on lifetime of ultra wide band wireless sensor networks

The asymptotic lower bounds on the lifetime of time hopping impulse radio ultra wide band (TH-IR UWB) wireless sensor networks are derived using percolation theory arguments. It is shown that for static dense TH-IR UWB wireless sensor network, which sensor nodes are distributed in a square of unit area according to a Poisson point process of intensity n, the lower bound on the lifetime is \( \Upomega \left( {\left( {{{\sqrt n } \mathord{\left/ {\vphantom {{\sqrt n } {\log \sqrt n }}} \right. \kern-\nulldelimiterspace} {\log \sqrt n }}} \right)^{\alpha - 2} } \right) \), where α > 2 is the path loss exponent, thus dense TH-IR UWB wireless sensor network is fit to be employed in large-scale network. For static extended TH-IR UWB wireless sensor network which sensor nodes are distributed in a square \( \left[ {0,\sqrt n } \right] \times \left[ {0,\sqrt n } \right] \) according to a Poisson point process of unit intensity, the lower bound on the lifetime is \( \Upomega \left( {{{\left( {\log \sqrt n } \right)^{2 - \alpha } } \mathord{\left/ {\vphantom {{\left( {\log \sqrt n } \right)^{2 - \alpha } } n}} \right. \kern-\nulldelimiterspace} n}} \right) \), therefore large-scale extended network will lead to shorten network lifetime. The results also indicate that the lower bound on the lifetime in the ideal case is longer than that of a static network by a factor of \( n^{1/2} \left( {\log \sqrt n } \right)^{\alpha - 4} \). Hence mobility of sensor nodes can improve network lifetime.     

Conductivity and Dielectric Relaxation Properties of Annealed Cr-Substituted Ni-Ferrite Nanoparticles

Nanocrystalline NiCr _x Fe_2?x O₄ spinel samples with x = 0.1 and 0.2 have been synthesized by coprecipitation method and annealed at 620°C and 1175°C for 4 h. Their electrical properties were investigated as functions of frequency in the range of 100 Hz to 100 kHz and temperature in the range of 308 K to 358 K. The dielectric constant (\( \varepsilon^{\prime } \)) and dielectric loss factor (\( {\hbox{tan}}\,\delta \)) appeared to decrease with increasing frequency, while the alternating-current (AC) conductivity (\( \sigma^{\prime } \)) increased. These dielectric parameters increased with increasing temperature. On the other hand, impedance spectroscopy gave Cole–Cole plots with only one semicircular arc for all the samples, indicating that the grain-boundary contribution was dominant in the conduction mechanism.     

A SiGe:C BiCMOS dual down converter for MIMO wireless infrastructure with configurable current consumption and linearity

This paper presents a dual RF down converter suitable for Multiple-Input and Multiple-Output infrastructure applications. The proposed architecture features a CMOS tapered buffer as local oscillator driver with a programmable supply voltage, provided by an embedded low dropout regulator. This approach allows scaling current consumption depending on linearity requirements. The RF path uses a balun with programmable tuning capacitors for single-to-differential signal conversion and \(50\text{-}\Omega\) input matching. A MOSFET passive mixer and a high-voltage (5 V) bipolar intermediate frequency amplifier complete the signal path. The circuit is fabricated in a SiGe:C BiCMOS process, occupies an area of \(2.8\, \text{mm} \, \times \, 2.5\, \text{mm}\), and has been assembled in a \(6\, \text{mm} \, \times \,6\, \text{mm}\), 40-pin, quad flat no-lead (QFN) package.     

Design considerations of CMOS active inductor for low power applications

Previous studies have shown that \(g_m/I_D\) (transconductance-to-drain-current) ratio based design is useful for optimizing analog circuits. In this paper, we explore challenges associated with designing a low-power active inductor. We focus in particular on sizing issues that arise as the transistor speed is maximized and the current consumption is minimized. Finally, we apply the results to design an amplifier integrated with an active inductor in \(0.18\,\upmu \hbox{m}\) CMOS process and show that by systematically working through sizing issues, a \(10\,\upmu \hbox{A}\) sub GHz amplifier can be designed.