A 0.18μm CMOS GAIN-SWITCHED LNA AND MIXER WITH LARGE DYNAMIC RANGE

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier(LNA) and a passive mixer with no external balun for near-zero-IF(Intermediate Frequency)/RF(Radio Frequency) applications are described.The LNA,fabricated in the 0.18μm 1P6M CMOS technology,adopts a gain-switched technique to increase the linearity and enlarge the dynamic range.The mixer is an IQ-based passive topology.Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω.Combining LNA and mixer,the front...     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

A low power high gain gain-controlled LNAC＋mixer for GNSS receivers

A low power high gain gain-controlled LNAC+mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load.Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNACmixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNAC+mixer, a previous low power LNAC+mixer, and the proposed LNAC+mixer are presented. The circuit is implemented in 0.18 m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2and consumes 2 mA current under 1.8 V supply.     

A RF receiver frontend for SC-UWB in a 0.18-μm CMOS process

正A radio frequency(RF) receiver frontend for single-carrier ultra-wideband(SC-UWB) is presented. The front end employs direct-conversion architecture,and consists of a differential low noise amplifier(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The proposed LNA employs source inductively degenerated topology.First,the expression of input impedance matching bandwidth in terms of gate-source capacitance, resonant frequency and target S_(11) is given.Then,a noise figure optimization strategy under gain and power constraints is proposed,with consideration of the integrated gate inductor,the bond-wire inductance,and its variation.The LNA utilizes two stages with different resonant frequencies to acquire flat gain over the 7.1-8.1 GHz frequency band,and has two gain modes to obtain a higher receiver dynamic range.The mixer uses a double balanced Gilbert structure.The front end is fabricated in a TSMC 0.18-/im RF CMOS process and occupies an area of 1.43 mm~2.In high and low gain modes,the measured maximum conversion gain are 42 dB and 22 dB,input 1 dB compression points are -40 dBm and -20 dBm,and S_(11) is better than -18 dB and -14.5 dB.The 3 dB IF bandwidth is more than 500 MHz.The double sideband noise figure is 4.7 dB in high gain mode.The total power consumption is 65 mW from a 1.8 V supply.     

一种带有25%占空比本振采用130 nmCMOS工艺应用于LTE直接变频无声表滤波器接收机设计

A CMOS long-term evolution(LTE) direct convert receiver that eliminates the interstage SAW filter is presented.The receiver consists of a low noise variable gain transconductance amplifier(TCA),a quadrature passive current commutating mixer with a 25%duty-cycle LO,a trans-impedance amplifier(TIA),a 7th-order Chebyshev filter and programmable gain amplifiers(PGAs).A wide dynamic gain range is allocated in the RF and analog parts.A current commutating passive mixer with a 25%duty-cycle LO improves gain,noise,and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference.Fabricated in a 0.13μm CMOS process,the receiver chain achieves a 107 dB maximum voltage gain,2.7 dB DSB NF(from PAD port),-11 dBm 11P3,and>+65 dBm UP2 after calibration,96 dB dynamic control range with 1 dB steps,less than 2%error vector magnitude(EVM) from 2.3 to 2.7 GHz.The total receiver(total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.     

一种应用于DRM/DAB调谐器的低噪声及dB线性中频可变增益放大器设计

A broadband CMOS intermediate frequency （IF） variable-gain amplifier （VGA） for DRM/DAB tuners is presented. The VGA comprises two cascaded stages： one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18μm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of-10 to 18 dB. It can operate in the frequency range of 30-700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is -3.9 dBm.     

A wide band up-conversion mixer for cable television tuner

An up-conversion mixer implemented in a 0.35μm SiGe BiCMOS technology for a double conversion cable TV tuner is described, The mixer converts the 100MHz to 1000MHz band to the Intermediate Frequency of 1GHz above. The mixer meets the linearity and noise figure requirements for a TV tuner. The noise figure （IF） of 19.2-17.5dB, ldB compression of 12.1dBm, and gain of-1-0.7dB in the 900MHz band are achieved at a supply voltage of 5V. The power consumption is 47mW.     

一种新型指数增益控制60dB可变增益放大器

A CMOS variable gain amplifier（VGA） that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved.The three-stage VGA with automatic gain control（AGC） and DC offset cancellation（DCOC） is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ±1 dB.The 3-dB bandwidth is over 8 MHz at all gain settings.The measured input-referred third intercept point（IIP3） of the proposed VGA varies from-18.1 to 13.5 dBm,and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz.The dynamic range of the closed-loop AGC exceeds 56 dB,where the output signal-to-noise-and-distortion ratio（SNDR） reaches 20 dB.The whole circuit,occupying 0.3 mm^2 of chip area,dissipates less than 3.7 mA from a 1.8-V supply.     

利用简单电阻偏置网络实现的高线性度电流驱动型无源混频器

A high linearity current communicating passive mixer including the mixing cell and transimpedance amplifier(TIA) is introduced.It employs the resistor in the TIA to reduce the source voltage and the gate voltage of the mixing cell.The optimum linearity and the maximum symmetric switching operation are obtained at the same time.The mixer is implemented in a 0.25μm CMOS process.The test shows that it achieves an input third-order intercept point of 13.32 dBm,conversion gain of 5.52 dB,and a single sideband noise figure of 20 dB.     

A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

正A fully integrated multi-mode multi-band directed-conversion radio frequency(RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented.The front-end employs direct-conversion design,and consists of two differential tunable low noise amplifiers(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The two independent tunable LNAs are used to cover all the four frequency bands,achieving sufficient low noise and high gain performance with low power consumption.Switched capacitor arrays perform a resonant frequency point calibration for the LNAs.The two LNAs are combined at the driver stage of the mixer,which employs a folded double balanced Gilbert structure,and utilizes PMOS transistors as local oscillator(LO) switches to reduce flicker noise.The front-end has three gain modes to obtain a higher dynamic range.Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface(SPI) module.The frontend is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm~2.The measured doublesideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.     

A reconfigurable passive mixer for multimode multistandard receivers in 0.18 μm CMOS

This paper presents a reconfigurable quadrature passive mixer for multimode multistandard receivers. By using controllable transconductor and transimpedance-amplifier stages, the voltage conversion gain of the mixer is reconfigured according to the requirement of the selected communication standard Other characteristics such as noises figure, linearity and power consumption are also reconfigured consequently. The design concept is verified by implementing a quadrature passive mixer in 0.18 μm CMOS technology. On wafer measurement results show that, with the input radio frequency ranges from 700 MHz to 2.3 GHz, the mixer achieves a controllable voltage conversion gain from 4 to 22 dB with a step size of 6 dB. The measured maximum ⅡP3 is 8.5 dBm and the minimum noise figure is 8.0 dB. The consumed current for a single branch (I or Q) ranges from 3.1 to 5.6 mA from a 1.8 V supply voltage. The chip occupies an area of 0.71 mm² including pads.     

一种用于数字电视接收机的58dB IRR CMOS镜像抑制混频器

The design,implementation,and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters（PPF） are presented.The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion.Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band.Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip,the mixer exhibits a high image rejection ratio（IRR） of 58 dB,a power consumption of 11 mW,and a 1-dB gain compression point of-15 dBm.     

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

This paper reports a wideband passive mixer for direct conversion multi-standard receivers.A brief comparison between current-commutating passive mixers and active mixers is presented.The effect of source and load impedance on the linearity of a mixer is analyzed.Specially,the impact of the input impedance of the transimpedance amplifier(TIA),which acts as the load impedance of a mixer,is investigated in detail.The analysis is verified by a passive mixer implemented with 0.18 m CMOS technology.The circuit is inductorless and can operate over a broad frequency range.On wafer measurements show that,with radio frequency(RF) ranges from 700 MHz to 2.3 GHz,the mixer achieves 21 dB of conversion voltage gain with a-1 dB intermediate frequency(IF) bandwidth of 10 MHz.The measured IIP3 is 9 dBm and the measured double-sideband noise figure(NF) is 10.6 dB at 10 MHz output.The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

Analysis and design of a 1.8-2.7 GHz tunable 8-band TDD LTE receiver front-end

This paper describes the analysis and design of a 0.13μm CMOS tunable receiver front-end that supports 8 TDD LTE bands,covering the 1.8-2.7 GHz frequency band and supporting the 5/10/15/20 MHz bandwidth and QPSK/16QAM/64QAM modulation schemes.The novel zero-IF receiver core consists of a tunable narrowband variable gain low-noise amplifier(LNA),a current commutating passive down-conversion mixer with a 2nd order low pass trans-impedance amplifier,an LO divider,a rough gain step variable gain pre-amplifier,a tunable 4th order Chebyshev channel select active-RC low pass filter with cutoff frequency calibration circuit and a fine gain step variable gain amplifier.The LNA can be tuned by reconfiguring the output parallel LC tank to the responding frequency band,eliminating the fixed center frequency multiple LNA array for a multi-mode receiver. The large various gain range and bandwidth of the analog baseband can also be tuned by digital configuration to satisfy the specification requirement of various bandwidth and modulation schemes.The test chip is implemented in an SMIC 0.13μm 1P8M CMOS process.The full receiver achieves 4.6 dB NF,-14.5 dBm out of band IIP3, 30-94 dB gain range and consumes 54 mA with a 1.2 V power supply.     

A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18μm CMOS

正This paper presents a wideband low noise amplifier(LNA) for multi-standard radio applications.The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gateinductive -peaking technique.High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band.Fabricated in 0.18μm CMOS process,the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain.The gain variation is within±0.8 dB from 300 MHz to 2.2 GHz.The measured noise figure(NF) and average HP3 are 3.4 dB and -2 dBm,respectively.The proposed LNA occupies 0.39 mm2 core chip area.Operating at 1.8 V,the LNA drains a current of 11.7 mA.     

An ultra-broadband distributed passive gate-pumped mixer in 0.18μm CMOS

A broadband distributed passive gate-pumped mixer(DPGM) using standard 0.18μm CMOS technology is presented.By employing distributed topology,the mixer can operate at a wide frequency range.In addition,a fourth-order low pass filter is applied to improve the port-to-port isolation.This paper also analyzes the impedance match and conversion loss of the mixer,which consumes zero dc power and exhibits a measured conversion loss of 9.4—17 dB from 3 to 40 GHz with a compact size of 0.78 mm~2.The input referred 1 dB compression point is higher than 4 dBm at a fixed IF frequency of 500 MHz and RF frequency of 23 GHz,and the measured RF-to-LO, RF-to-IF and LO-to-IF isolations are better than 21,38 and 45 dB,respectively.The mixer is suitable for WLAN, UWB,Wi-Max,automotive radar systems and other millimeter-wave radio applications.     

应用于2.4GHz无线传感网的超低功耗射频接收前端设计

This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network （WSN） in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate （CG） LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure （NF） at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point （IPldB） at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.     

A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop

A low voltage low power CMOS limiter and received signal strength indicator(RSSI) with an integrated automatic gain control(AGC) loop for a short-distance receiver are implemented in SMIC 0.13μm CMOS technology.The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within i0.5 dB for an input power from -65 to -8 dBm.The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA(I and Q paths) from a 1.2 V supply.Auto LNA gain mode selection with a combined RSSI function is also presented.Furthermore,with the compensation circuit,the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics.