基于电流模式的硅像素探测器前端读出ASIC设计

针对应用于同步辐射的硅像素探测器,设计了一种基于电流模式的像素型前端读出单元电路,像素单元电路主要包括电荷灵敏前置放大器、跨导放大器、电流甄别器、阈值调节电路和计数器等,实现了信号放大、电压转为电流、信号甄别以及计数等功能。芯片基于SMIC 0.13μm/1.2V CMOS工艺设计,像素单元面积为100μm×100μm,仿真结果表明:像素单元静态功耗为50μW,等效噪声电荷低于100e-,不一致性小于100e-,能量甄别范围为8 ke V~20 ke V,达到了预期设计目标。与电压模式的像素单元电路相比,具有结构简单、功耗低、芯片面积小以及抗干扰能力强的特点。     

BESⅢ升级中硅像素径迹室位置校准的MC研究

硅像素径迹室是BESⅢ升级项目之一,离线软件校准是其离线数据处理系统的重要组成部分,研究过程采用蒙特卡罗方法,将残差法应用于漂移室升级项目中硅像素径迹室的几何位置校准,分别以ladder、芯片为最小探测单元进行研究,结果表明,该方法可有效应用于硅像素径迹室的位置校准。     

SOI像素探测器的COB组装工艺初步研究

从子板PCB设计、芯片粘接、优化引线键合参数方面对SOI像素探测器的COB组装工艺做了初步研究。基板焊盘表面处理选用了电镀化学镍钯金的工艺,并对焊盘排布方式做了改进;芯片粘接选用了导电环氧树脂胶,探讨了水平定位误差和垂直定位误差对键合的影响及处理方法;通过反复试验和不断优化得出一套引线键合优化参数。对子板模块性能测试表明:其噪声和漏电流水平均保持在合理范围。COB组装技术可为后续的硅像素探测器芯片拼接提供技术支撑。     

BESⅢ主漂移室内室升级MAPS芯片探针台测试系统设计

为满足北京谱仪Ⅲ主漂移室内室升级MAPS芯片测试需要,设计了一套用于芯片功能检查的芯片探针台测试系统。该系统实现了批量芯片JTAG通讯、芯片功耗、像素箝位电压、读出数据等芯片的功能检查,并可以进行芯片噪声水平以及甄别器阈值扫描等初步测试。芯片的探针台测试不仅在非邦定的情况下完成了芯片的筛选,同时可为后续芯片在探测器上工作时的阈值等参数配置提供参考。     

CMOS硅像素探测器测试系统设计

针对环形正负电子对撞机(CEPC)最内层的顶点探测器而研制的CMOS硅像素探测器已经提交首次流片。为了采集探测器的数据进而研究前端芯片的性能,基于现场可编程逻辑门阵列(FPGA)设计高速数据传输的测试系统,该系统以PCI Express总线模式进行高速传输数据。对系统性能的测试表明:数据传输速度能达到6Gb/s,传输的数据量和误码率性能均满足CMOS硅像素探测器芯片的测试要求。     

多层像素芯片缪子成像装置中芯片位置校正方法研究

硅像素互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)芯片因具有微米级的位置分辨能力和极高的探测效率等特点,对于径迹精确重建具有举足轻重的作用。通过大面积拼接,能够将硅像素芯片用于μ子成像,但芯片拼接产生的机械误差,以及各层之间的相对位置误差,对μ子重建过程中的位置精度具有明显影响。本文利用μ子通过探测层时产生的观测点,建立了基于μ子径迹直线拟合模型的迭代芯片位置校正算法。通过在GEANT4程序中构建μ子成像探测原型装置,其中包含8个物理探测层,每层拼接了4块硅像素芯片,并添加芯片在x、y方向与旋转角θ三个自由度上的偏移量,模拟了真实情况下的机械误差对重建位置精度的影响。结果显示:该算法可用于芯片真实位置的高精度修正,使芯片位置修正精度小于5μm。     

脉冲激光模拟SRAM器件单粒子翻转效应的试验方法研究

针对0.13 μm和0.35 μm工艺尺寸的两款商用SRAM器件进行了脉冲激光背部单粒子翻转效应试验方法研究。单粒子翻转效应主要测试单粒子翻转阈值和单粒子翻转截面,本文主要研究了激光聚焦深度、激光脉冲注量、测试模式和芯片配置的数据对测试两者的影响。试验结果表明：只有聚焦到芯片有源区才可测得最低的翻转阈值和最大的翻转截面,此时的结果与重离子结果基本一致;注量对翻转阈值测试无影响,但注量增大时翻转截面会减小,测试时激光脉冲注量应小于1×10⁷cm^-2;测试模式和存储数据对翻转阈值和翻转截面的影响不大,测试时可不考虑。     

基于商用工艺的抗辐射触发器单元设计

修改芯片中的电路拓扑结构以及版图结构实现抗辐射性能,并最终通过商用半导体工艺制造线生产抗辐射芯片是目前抗辐射设计的一个重要思路。论文结合双互锁单元技术(DICE)、空间冗余技术(TMR)、时间滤波技术(TS)和RC滤波技术4种加固技术,完成抗辐射D触发器单元设计。最后通过理论分析和模拟仿真验证其抗辐射性能。     

脉冲核磁共振硬脉冲序列发生器的设计

以C8051F020单片机为核心控制单元,控制DDS芯片AD9850和CPLD芯片EPM7512AETC144-10,设计了应用于脉冲核磁共振装置中的硬脉冲序列生成器,能产生IR和CPMG等硬脉冲序列,适用于0.6T及以下的主场装置.实验表明,该设计具有稳定性好,自动化程度优良和性价比良好的特点,具有很高的实用价值.     

基于APV25多通道读出电子学系统设计

介绍了基于APV25芯片的多通道读出电子学系统的设计方法,利用ASIC芯片与可扩展读出系统相结合,实现多通道信号的处理。在该系统中,基于PXI机箱的单个读出板可实现2 048路信号的读出及处理,并具有集成度高、低功耗、可扩展等优点。电子学测试结果表明,本系统电荷输入线性动态范围为0~12 fC,APV25等效输入噪声408 e,可适应大型物理实验微结构气体探测器、硅像素探测器等探测器的读出需求。     

A versatile 16-channel front-end integrated circuit for semiconductor radiation detectors

A CMOS front-end integrated circuit consisting of 16 identical analog channels is proposed for semiconductor radiation detectors. Each of the 16 channels has a low noise charge sensitive amplifier, a pulse shaper, a peak detect and hold circuit and a discriminator, while analog voltage and channel address are routed off the chip. It can accommodate both electron and hole collection with selectable gain and peaking time. Sequential and sparse readout, combining with self-trigger and external trigger, makes four readout modes. The circuit is implemented in a 0.35 μm DP4M (double-poly-quad-metal) CMOS technology with an area of 2.5×1.54 mm2 and power dissipation of 60 mW. A single channel chip is tested with Verigy 93000. The gain is adjustable from 13 to 130 mV·fC–1 while the peaking time varies between 0.7 and 1.6 μs. The linearity is more than 99% and the equivalent noise charge is about 600e.     

基于APV25读出电子学系统的GEM探测器的位置分辨与X射线成像研究

采用3层GEM膜制作了有效面积为10 cm×10 cm的GEM探测器,该探测器采用二维条读出方式,条间距为400 μm,每个维度有256个读出通道。探测器的读出采用APV25读出电子学系统,根据GEM探测器的需要,设计并改进了电子学系统使用的背板连接器。实验测得GEM探测器空间分辨为76 μm。进行了X射线二维成像研究,获得了清晰的二维图像,探测器与电子学运行稳定可靠。     

Digital Architecture and Interface of the New ATLAS Pixel Front-End IC for Upgraded LHC Luminosity

A new pixel front-end integrated circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel front-end. The new digital architecture logic is not based on a transfer of all pixel hits to the periphery of the chip, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the double-column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.     

A MCM-D-type module for the ATLAS pixel detector

For the ATLAS experiment at the planned Large Hadron Collider (LHC) at CERN hybrid pixel detectors are being built as innermost layers of the inner tracking detector system. Modules are the basic building blocks of the ATLAS pixel detector. A module consists of a sensor tile with an active area of 16.4 mm×60.4 mm, 16 read out ICs, each serving 24×160 pixel unit cells, a module controller chip, an optical transceiver and the local signal interconnection and power distribution busses. The dies are attached by flip-chip assembly to the sensor diodes and the local busses. In the following a module based on MCM-D technology will be discussed and prototype results will be presented     

Low-Power Amplifier-Discriminators for High Time Resolution Detection

Low-power amplifier-discriminators based on a so-called NINO architecture have been developed with high time resolution for the readout of radiation detectors. Two different circuits were integrated in the NINO13 chip, processed in IBM 130 nm CMOS technology. The LCO version (Low Capacitance and consumption Optimization) was designed for potential use as front-end electronics in the Gigatracker of the NA62 experiment at CERN. It was developed as pixel readout for solid-state pixel detectors to permit minimum ionizing particle detection with less than 180 ps rms resolution per pixel on the output pulse, for power consumption below 300 muW per pixel. The HCO version (High Capacitance Optimization) was designed with 4 mW power consumption per channel to provide timing resolution below 20 ps rms on the output pulse, for charges above 10 fC. Results presented show the potential of the LCO and HCO circuits for the precise timing readout of solid-state detectors, vacuum tubes or gas detectors, for applications in high energy physics, bio-technologies or medical imaging.     

Position sensitive photon counting with an ISPA tube

The newly developed Imaging Silicon Pixel Array (ISPA) tube consists of a photocathode viewed at a 30-mm distance by a silicon chip, which contains 1024 pixels with 75 μm×500 μm edges. With this tube we imaged, as an example of a weak light source, β-tracks (⁹⁰Sr) traversing a fused square bundle (2.5 mm edges), which contains 1600 individual scintillating fibers of 60-μm transverse dimension. Simultaneously we counted the number of photoelectrons/mm (hit density) at different source positions along the 2-m fiber bundle, with potential differences varying from 10 kV to 26 kV between photocathode and pixel anode of the ISPA tube, and at different threshold settings of the pixel chip. The obtained hit densities are compared with those measured with a Hybrid Photomultiplier Tube (HPMT), which contains a silicon pin diode as anode instead of a pixel chip     

FCM燃料堆内行为模拟及结构设计研究

The thermal mechanical performance of the fully ceramics microencapsulated fuel (FCM) with different non-fuel part size was simulated using two-dimensional characteristic unit. When the fissile loading meet the requirements of the reactor core, the stress condition of SiC matrix and SiC layers were investigated for FCM pellets with different structures. Non-fuel parts and SiC layers suffered relative lower stress by optimizing FCM pellet structure and adjusting distance between different TRISO particles. The stress distribution of matrix, non-fuel part and SiC layer was discussed for the FCM pellets with non-fuel part size from 100 μm to 500 μm. The results indicate that, the maximum hoop stress of the matrix and SiC layer increased with the increasing of non-fuel part size, while the non-fuel parts exhibited crosscurrent. Non-fuel parts and SiC layer possessed lower stress when the non-fuel part was 400 μm. The stress of non-fuel part was about 400 MPa, and the maximum hoop stress of the SiC layers were about 200 MPa. The failure probability was 2.5×10-4. The structure integrity was maintained for the pellets with 400 μm non-fuel part, at the same time the failure probability SiC layer was low. Structural optimization is the basis for the application of FCM pellet.     

Study of performance of small gamma camera consisting of crystal pixel array and position sensitive photomultiplier tube

1 Introduction In recent years a great effort has been made in developing compact gamma camera to improve nu-clear medical imaging. Conventional Anger gamma camera[1] uses a NaI(Tl) scintillator block and an array of photomultiplier tube. It has large size and poor spa-tial resolution, thus it is not suitable for small object image. Though the gamma camera using planar crystal coupled with position sensitive photomultiplier tube (PSPMT[2]) could greatly improve spatial resolu-tion,[3-5] pl…     

FCM燃料堆内行为模拟及结构设计研究

本文采用二维特征模型模拟不同无燃料区厚度全陶瓷微封装弥散（FCM）燃料的热力学行为,在保证堆芯装载要求的条件下,研究不同结构FCM燃料SiC基体和包覆燃料颗粒SiC层的应力状态。通过优化无燃料区厚度,调整TRISO颗粒间的间距,保证无燃料区和SiC层同时具有较低的应力水平。分析了无燃料区厚度为100 ~ 500 μm时基体SiC、无燃料区以及SiC层的应力分布,结果表明,基体SiC和SiC层最大应力随无燃料区厚度增大而增大,而无燃料区的最大应力则随其厚度增大而降低。当无燃料区厚度为400 μm时,无燃料区和SiC层均处于较低的应力状态,无燃料区SiC基体应力约为400 MPa,而SiC层的最大环向应力约为200 MPa,其失效概率约为2.5×10-4。因此,当无燃料区厚度为400 μm时,FCM燃料既能维持芯块结构完整,又能保证SiC层具有较低的失效概率。结构优化为FCM燃料的应用提供了基础。      

CMOS工艺X射线图像传感器设计

本文设计了一种不需闪烁体或增感屏,直接对X射线进行探测成像的线阵图像传感器,对其电荷收集进行了理论分析,设计了辐射加固的光敏元结构。采用0.5 μm DPTM CMOS工艺,针对单个像元内含不同个数光敏元的结构进行了流片和X射线实验测试。测试结果表明：该图像传感器暗信号电压约为1 V,随像元内光敏元个数的增加暗信号电压增大;饱和输出电压为2.4 V;随光敏元个数的增加,电荷收集总量增加,总寄生电容也同时增加,所设计的单个像元含3个光敏元的结构能得到相对更大的有效输出电压。