Design of sequential circuits by quantum-dot cellular automata

This paper proposes a detailed design analysis of sequential circuits for quantum-dot cellular automata (QCA). This analysis encompasses flip-flop (FF) devices as well as circuits. Initially, a novel RS-type FF amenable to a QCA implementation is proposed. This FF extends a previous threshold-based configuration to QCA by taking into account the timing issues associated with the adiabatic switching of this technology. The characterization of a D-type FF as a device consisting of an embedded wire is also presented. Unique timing constraints in QCA sequential logic design are identified and investigated. An algorithm for assigning appropriate clocking zones to a QCA sequential circuit is proposed. A technique referred to as stretching is used in the algorithm to ensure timing and delay matching. This algorithm relies on a topological sorting and enumeration step to consistently traversing only once the edges of the graph representation of the QCA sequential circuit. Examples of QCA sequential circuits are provided.     

On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire

Among emerging technologies, Quantum-dot Cellular Automata (QCA) relies on innovative computational paradigms. For nano-scale implementation, the so-called processing-by-wire (PBW) paradigm in QCA is very effective as processing takes place, while signal communication is accomplished. This paper analyzes the defect tolerance properties of PBW for manufacturing tiles by molecular QCA cells. Based on a 3?×?3 grid and various input/output arrangements in QCA cells, different tiles are analyzed and simulated using a coherence vector engine. The functional characterization and polarization level of these tiles for undeposited cell defects are reported and detailed profiles are provided. It is shown that novel features of PBW are possible due to the spatial redundancy of the cells in the tiles that permits to retain at high probability the fault free function in the presence of defects. Moreover, it is shown that QCA tiles are robust and inherently tolerant to cell defects (by logic equivalence, also additional cell defects can be accommodated).     

量子元胞自动机器件和电路的研究进展

量子元胞自动机(QCA)是一种新颖的纳米技术,该技术不再通过电流或电压而是基于场相互作用进行信息的计算和传递。首先,综述了两种量子元胞自动机(EQCA和MQCA)器件的计算原理、基本逻辑门和时钟。指出了QCA元胞构成的不同线结构可在相同层交叉传递信号而不受影响。然后,进一步总结了制备QCA器件和功能阵列或电路的实验方法和材料,得出MQCA器件和分子EQCA器件的发展将使该器件逐步达到实际应用水平的结论。详细讨论了目前QCA器件和电路(尤其是存储单元结构)研究取得的重要进展以及面临的问题。提出了QCA器件未来理论和应用研究中的开放课题和方向。     

Analytical method for cell displacement defect quantum-dot cellular automata primitive

Quantum-dot cellular automata (QCA) is an emerging computational paradigm which can overcome scaling limitations of the existing complementary metal oxide semiconductor (CMOS) technology. The existence of defects cannot be ignored, considering the fabrication of QCA devices at the molecular level where it could alter the functionality. Therefore, defects in QCA devices need to be analyzed. So far, the simulation-based displacement defect analysis has been presented in the literature, which results in an increased demand in the corresponding mathematical model. In this paper, the displacement defect analysis of the QCA main primitive, majority voter (MV), is presented and carried out both in simulation and mathematics, where the kink energy based mathematical model is applied. The results demonstrate that this model is valid for the displacement defect in QCA MV.     

QCA Circuits for Robust Coplanar Crossing

In this paper, different circuits of Quantum-dot Cellular Automata (QCA) are proposed for the so-called coplanar crossing. Coplanar crossing is one of the most interesting features of QCA because it allows for mono-layered interconnected circuits, whereas CMOS technology needs different levels of metalization. However, the characteristics of the coplanar crossing make it prone to malfunction due to thermal noise or defects. The proposed circuits exploit the majority voting properties of QCA to allow a robust crossing of wires on the Cartesian plane. This is accomplished using enlarged lines and voting. A Bayesian Network (BN) based simulator is utilized for evaluation; results are provided to assess robustness in the presence of cell defects and thermal effects. The BN simulator provides fast and reliable computation of the signal polarization versus normalized temperature. Simulation of the wire crossing circuits at different operating temperatures is provided with respect to defects and a quantitative metric for performance under temperature variations is proposed and assessed.     

QCA电路的缺陷研究

针对量子元胞自动机电路中出现的元胞移位等元胞缺陷,介绍了基于QCADesigner的元胞缺陷分析,得出了特定结构的容错范围。对于制造过程出现的单电子故障,分析了不同输入时单电子故障对传输线和反相器的影响。对于制造过程中出现的漂移电荷缺陷,分析了这些缺陷对传输线的影响。通过改变元胞与传输线之间的距离,研究了QCA传输线之间的串扰问题,得出了其容错范围。最后对RS触发器中出现的元胞缺陷采用测试序列进行了分析研究,从而为进一步研究QCA电路的缺陷提供了依据和方向。     

Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA

An extensive literature exists on the mathematical characterization of reversible logic. However, the possible technological basis of this computing paradigm still remains unsolved. In this paper, quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (referred to as QCA1 and QCA2) are proposed. These gates are compared (in terms of delay, area and logic synthesis) with other reversible gates (such as Toffoli and Fredkin) for QCA implementation. Due to the expected high error rates in nano-scale manufacturing, testing of nano devices, including QCA, has received considerable attention. The focus of this paper is on the testability of a one-dimensional array made of QCA reversible gates, because the bijective nature of reversible gates significantly facilitates testing of arrays. The investigation of testability relies on a fault model for molecular QCA that is based on a single missing/additional cell assumption. It is shown that C-testability of a 1D reversible QCA gate array can be guaranteed for single fault. Theory and circuit examples show that error masking can occur when multiple faults are considered.     

A Test Generation Framework for Quantum Cellular Automata Circuits

In this paper, we present a test generation framework for quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted recent significant attention and shows promise as a viable future technology. This work is motivated by the fact that the stuck-at fault test set of a circuit is not guaranteed to detect all defects that can occur in its QCA implementation. We show how to generate additional test vectors to supplement the stuck-at fault test set to guarantee that all simulated defects in the QCA gates get detected. Since nanotechnologies will be dominated by interconnects, we also target bridging faults on QCA interconnects. The efficacy of our framework is established through its application to QCA implementations of MCNC and ISCAS'85 benchmarks that use majority gates as primitives     

Adder design using 5-input majority gate in a novel “Multilayer Gate Design Paradigm” for Quantum Dot Cellular Automata Circuits

This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input-output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact.     

Multiple Missing Cell Defect Modeling for QCA Devices

Considering the limitations of CMOS technology, the Quantum-dot Cellular Automata (QCA) is emerging as one of the alternatives for Integrated Circuit (IC) Technology. A lot of work is being carried out for design, fabrication and testing of QCA circuits. In this paper, we have worked on defect analysis, fault models development and deriving various properties for QCA Majority Voter (MV) to effectively generate the test patterns for QCA circuits. It has been shown that unlike CMOS technology, single missing cell consideration is not enough for QCA technology. We have presented that the Multiple Missing Cell (MMC) defect, which is very natural at nanoscale, causes the sizable difference in functionality compared to Single Missing Cell consideration described in literature, and hence, must be considered while test generation. The proposed MMC is supported by exhaustive simulation results as well as kink energy based mathematical analysis. Further, Verilog fault models are proposed which can be used for the functional, timing verification and activation of faults caused by MMC defect. The effect of MMC on output is analyzed in stand-alone MV as well as when MV is a part of circuit. At the end, we have proposed the test properties of MV when being used as MV itself, as AND gate or OR gate. These properties may be further helpful in development of test generation algorithms.     

脉冲异步时序电路分析与设计中应注意的两个问题

讨论了脉冲异步时序电路分析与设计中的一些问题,指出了状态信号反馈对触发器时钟信号的影响和传输延迟状态转换的影响。     

Basic circuits for multi-valued sequential logic

Multi-valued logic circuits were presented as an alternative to well known binary logic. It has the potential of reducing the number of active elements and interconnection lines. More data may be transferred trough a single wire using logic signals having more than two levels. However, in spite of their potential advantages, developments in multi-valued systems are not satisfactory. In particular, it is very difficult to find circuits to implement the multilevel sequential circuits. The flip-flop is the basic building block of sequential circuits and may be used to design sequential circuits such as counter/dividers and other sequential circuits. In this regard, a new multilevel flip-flop, called the AB flip-flop, was developed and published by the authors recently (Sarica and Morgul, Electron Lett 47(5):297–298, 2011). In this paper we present a new latch and restoration circuit which improves the performance of the previously designed flip-flop circuit. It is also shown that any sequential circuit may be implemented by using this flip-flop.     

Design metal-dot based QCA circuits using SPICE model

This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulating the basic logic gates such as inverter and majority voter. The proposed model makes it possible to design and simulate QCA combinational circuits and hybrid circuits of QCA and other NANO devices using SPICE. In the second half part of the paper, SET and QCA co-design methodology is proposed and SET is used as a readout interface of the QCA cell array. The SET and QCA hybrid circuit is a promising nano-scale solution.     

Design of testable reversible latches by using a novel efficient implementation of Fredkin gate

ABSTRACT

Energy dissipation caused by information loss in irreversible computations will be an important limitation for the development of nano-scale circuits in the near future. Reductions in energy dissipation comprise one of the important goals of nanotechnology-based methods, including Quantum dot Cellular Automata (QCA), and so it is desirable to consider reversibility in the design of QCA circuits. In this research, a novel reversible Fredkin gate based on QCA is proposed, which is more efficient and less complex than the conventional Fredkin gate. Conservative reversible logic is parity preserving; hence, any permanent or transient fault can be caused a mismatch between the inputs and the outputs and can be concurrently detected if a reversible circuit is implemented with the conservative Fredkin gate. A single missing/additional cell defect is investigated in the proposed Fredkin gate and fault patterns are presented. To demonstrate the efficiency of the proposed design, some testable reversible sequential elements, such as D-latch, JK-latch, T-latch and SR-latch, are designed by using it. Our proposed concurrent testable designs greatly reduce the occupied area and maximise the circuit density in comparison with previously reported designs. The proposed designs are simulated and verified using QCA Designer ver.2.0.3 and HDLQ.     

Coplanar QCA crossovers

Quantum-dot cellular automata (QCA) is one of the promising nextgeneration fabrics for circuits. Coplanar wire crossings are one of the more elegant features of this new low-power computing paradigm. Proposed are coplanar wire crossovers using a single type of QCA cells, which has significant implications in fabrication and fault tolerance.     

Using nano-scale QCA technology for designing fault-tolerant 2:1 multiplexer

Recently, Quantum-dot Cellular Automata (QCA) has appeared as a noteworthy substitution to CMOS technology. It contains ultra-high-velocity, efficient energy, low area for design circuits, one potential computational fabric for Nano computing systems, and integration density. On the other hand, fault-tolerant circuits promise reliability circuits by computation redundancy cells. This work targets to form two designs of fault-tolerant 2:1 multiplexer in the QCA framework. This proposed QCA multiplexer designs use cell redundancy on the wire, NOT gates, and majority gates. The coplanar structures for the proposed 2:1 QCA fault-tolerant multiplexers are provided and operated based on cell interactions. Four types of faults, cell misalignment, cell missing, cell displacement, and extra cell, are essential in analyzing the fault attributes. The proposed fault-tolerant multiplexers can attain 100% fault-tolerance while extra cell deficiencies or single missing exist in the layout of the QCA. The simulation outcomes reached by the software, QCA Designer 2.0.3, approve that the suggested multiplexers work correctly and can be utilized in QCA technology as a high-performance schematization. The outcomes show that the proposed construct outperforms any prior schematization.

     

低功耗双边沿触发器的逻辑设计

本文从消除时钟信号冗余跳变而致的无效功耗的要求出发,提出双边沿触发器的设计思想与基于与非门的逻辑设计．用ＰＳＰＩＣＥ程序模拟证实了该种触发器具有正确的逻辑功能,能够正常地应用于时序电路的设计,并且由于时钟工作频率减半而导致系统功耗的明显降低．     

Reliability analysis of magnetic logic interconnect wire subjected to magnet edge imperfections

Nanomagnet logic (NML) devices have been proposed as one of the best candidates for the next generation of integrated circuits thanks to its substantial advantages of nonvolatility,radiation hardening and potentially low power.In this article,errors of nanomagnetic interconnect wire subjected to magnet edge imperfections have been evaluated for the purpose of reliable logic propagation.The missing comer defects of nanomagnet in the wire are modeled with a triangle,and the interconnect fabricated with various magnetic materials is thoroughly investigated by micromagnetic simulations under different comer defect amplitudes and device spacings.The results show that as the defect amplitude increases,the success rate of logic propagation in the interconnect decreases.More results show that from the interconnect wire fabricated with materials,iron demonstrates the best defect tolerance ability among three representative and frequently used NML materials,also logic transmission errors can be mitigated by adjusting spacing between nanomagnets.These findings can provide key technical guides for designing reliable interconnects.     

Design and comparison of new fault-tolerant majority gate based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption.However,in the manufacture of nanoscale devices prone to various forms of defects,which will affect the subsequent circuits design.Therefore,fault-tolerant QCA architectures have become a new research direction.The purpose of this paper is to build a novel fault-tolerant three-input majority gate based on normal cells.Compared with the previous structures,the majority gate shows high fault tolerance under single-cell and double-cell omission defects.In order to examine the functionality of the proposed structure,some physical proofs under single cell missing defects are provided.Besides,two new fault-tolerant decoders are constructed based on the proposed majority gate.In order to fully demonstrate the performance of the proposed decoder,the previous decoders were thoroughly compared in terms of fault tolerance,area and delay.The result shows that the proposed design has a good fault tolerance characteristic,while the performance in other aspects is also quite good.     

基于多β晶体管的双边沿D触发器及其应用

通过对多 β晶体管的开关特性分析 ,结合其射极输入、射极输出、高速工作等特点设计了二值双边沿 D触发器 ,计算机模拟表明该设计具有正确的逻辑功能和高速的工作特性。文中还介绍了双边沿 D触发器在时序电路中的应用。