Compact Wide Stopband Ultra Wideband Bandpass Filter Using Multilayer Liquid Crystal Polymer Technology

Novel ultra-wideband (UWB) bandpass filters (BPFs) are proposed based on broadside coupled capacitive-loaded transmission line resonators (C-L TLR) in this letter. By utilizing the wideband harmonic suppression behavior of C-L TLR, the proposed UWB BPFs were designed with wide stopband and implemented using multilayer organic liquid crystal polymer (LCP) technology. As demonstrations, a vialess five-pole BPF was designed first, and then by adopting shunt short-circuited microstrip stubs at input/output ports, a compact UWB BPF was designed to meet FCC-defined UWB indoor mask. The proposed UWB BPFs were fabricated using multilayer LCP technology. Good agreements between simulated and measured results of fabricated filters were observed. The measured results show that the fabricated BPFs have good selectivity, wide stopband and high rejection level. The fabricated UWB BPFs have compact sizes of 15.15 mm by 4.7 mm (about $0.55lambda_{rm g0}$ by $0.17lambda_{rm g0}$); and 9.6 mm by 9.2 mm (about $0.35lambda_{rm g0}$ by $0.33lambda_{rm g0}$), respectively, where $lambda_{rm g0}$ is the guided wavelength of $50~Omega$ microstrip line at 6.85 GHz. They are attractive for UWB communications and radar systems.      

Highly Integrated Ka-Band Sub-Harmonic Image-Reject Down-Converter MMIC

An integrated compact down-converter monolithic microwave integrated circuit chip is presented. It is designed using anti-parallel diode pair sub-harmonic image reject mixer and RF low noise amplifier. The quasi-lumped circuit components are employed in circuit design for the compact chip size. The conversion gain of the chip is 10–14 dB, image rejection above 20 dBc, and noise figure of 3.5–4.5 dB for the RF frequency of 29–36 GHz. The chip size is as compact as $2.24~{rm mm}^{2}$ on a $100~mu{rm m}$ GaAs substrate thickness.      

A Single-Ended Fully Integrated SiGe 77/79 GHz Receiver for Automotive Radar

A single-ended 77/79 GHz monolithic microwave integrated circuit (MMIC) receiver has been developed in SiGe HBT technology for frequency-modulated continuous-wave (FMCW) automotive radars. The single-ended receiver chip consists of the first reported SiGe 77/79 GHz single-ended cascode low noise amplifier (LNA), the improved single-ended RF double-balanced down-conversion 77/79 GHz micromixer, and the modified differential Colpitts 77/79 GHz voltage controlled oscillator (VCO). The LNA presents 20/21.7 dB gain and mixer has 13.4/7 dB gain at 77/79 GHz, and the VCO oscillates from 79 to 82 GHz before it is tuned by cutting the transmission line ladder, and it centres around 77 GHz with a tuning range of 3.8 GHz for the whole ambient temperature variation range from $- hbox{40},^{circ}{hbox{C}}$ to $+ hbox{125},^{circ}{hbox{C}}$ after we cut the lines by tungsten-carbide needles. Phase noise is $-$90 dBc/Hz@1 MHz offset. Differential output power delivered by the VCO is 5 dBm, which is an optimum level to drive the mixer. The receiver occupies 0.5 ${hbox{mm}}^{2}$ without pads and 1.26 ${hbox{mm}}^{2}$ with pads, and consumes 595 mW. The measurement of the whole receiver at 79 GHz shows 20–26 dB gain in the linear region with stable IF output signal. The input ${rm P}_{rm 1dB}$ of the receiver is $-$35 dBm.      

70 GHz Folded Loop Dual-Mode Bandpass Filter Fabricated Using 0.18 $mu$ m Standard CMOS Technology

This letter presents the design and implementation of a 70 GHz millimeter-wave compact folded loop dual-mode on-chip bandpass filter (BPF) using a 0.18 $mu$m standard CMOS process. A compact BPF, consisting of such a planar ring resonator structure having dual transmission zeros was fabricated and designed. The size of the designed filter is 650$,times,$ 670 $mu$ m$^{2}$ . Calculated circuit model, EM simulated and measured results of the proposed filter operating at 70 GHz are shown in a good agreement and have good performance. The filter has a 3-dB bandwidth of about 18 GHz at the center frequency of 70 GHz. The measured insertion loss of the passband is about 3.6 dB and the return loss is better than 10 dB within the passband.      

180$^{circ}$ and 90$^{circ}$ Phase Shifting Networks With an Octave Bandwidth and Small Phase Errors

A new phase shifting network for both 180 $^{circ}$ and 90 $^{circ}$ phase shift with small phase errors over an octave bandwidth is presented. The theoretical bandwidth is 67% for the 180$^{circ}$ phase bit and 86% for the 90$^{circ}$ phase bit when phase errors are $pm 2^{circ}$. The proposed topology consists of a bandpass filter (BPF) branch, consisting of a LC resonator and two shunt quarter-wavelength transmission lines (TLs), and a reference TL. A theoretical analysis is provided and scalable parameters are listed for both phase bits. To test the theory, phase shifting networks from 1 GHz to 3 GHz were designed. The measured phase errors of the 180$^{circ}$ and the 90$^{circ}$ phase bit are $pm 3.5^{circ}$ and $pm 2.5^{circ}$ over a bandwidth of 73% and 102% while the return losses are better than 18 dB and 12 dB, respectively.      

A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

A Short Range, Low Data Rate, 7.2 GHz-7.7 GHz FM-UWB Receiver Front-End

A 9 mW FM-UWB receiver front-end for low data rate ( $≪$$ hbox{50~kbps}$), short range ( $≪$$hbox{10~m}$) applications operating in the ultra-wideband (UWB) band centered at 7.45 GHz is described in this paper. A single-ended-to-differential preamplifier with 30 dB voltage gain, a 1 GHz bandwidth FM demodulator, and a combined (preamp/demodulator) receiver front-end were fabricated in 0.25 $muhbox{m}$ SiGe:C BiCMOS and characterized. Measured receiver sensitivity is $-hbox{85.8~dBm}$ while consuming 9 mW from a 1.8 V supply, and $-hbox{83~dBm}$ consuming 6 mW at 1.5 V. 15-20 m range line-of-sight in an indoor environment is realized, justifying FM-UWB as a robust radio technology for short range, low data rate applications. Multi-user and interference capabilities are also evaluated.      

A 26–38 GHz Monolithic Doubly Balanced Mixer

A novel configuration of doubly balanced mixer is presented for operating over the 26–38 GHz band. The monolithic microwave integrated circuit (MMIC) was implemented by GaAs 0.15 $mu$ m pHEMT technology with the compact size of 1 $,times,$2.5 mm $^{2}$. A 180 $^circ$ hybrid circuit and two identical Marchand baluns were employed to achieve good port-to-port isolation. They also have wide band performance, make the mixer more compact, and simplify IF extraction. This mixer has a conversion loss of better than 6 dB, a dc-10 GHz IF bandwidth, and the LO-to-RF and LO-to-IF isolations are better than 20 dB and 29 dB, respectively.      

A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS

The commercial potential of the 60 GHz band, in combination with the scaling of CMOS, has resulted in a lot of plain digital CMOS circuits and systems for millimeter-wave application. This work presents a 90 nm digital CMOS two-path 52 GHz phased-array receiver, based on LO phase shifting. The system uses unmatched cascading of RF building blocks and features gain selection. A QVCO with a wide tuning range of 8 GHz is demonstrated. The receiver achieves 30 dB of maximum gain and 7.1 dB of minimum noise figure per path around 52 GHz, for a low area and power consumption of respectively 0.1 ${hbox{mm}}^{2}$ and 65 mW. The presented receiver targets 60 GHz communication where beamforming is required.      

Parallel coupled-line bandpass filter with branch-line shape for g-band frequency

A parallel coupled-line planar bandpass filter (BPF) with branch-line shape using coplanar waveguide technology on GaAs substrate is presented. The unit parallel coupled-line BPF utilises a parallel coupled-line resonator with an open-ended stub which has suppression response of spurious band. Four unit parallel coupled-line BPFs are integrated with branch-line shape and open-circuit stubs on input and output ports are also integrated for improvement of rejection performance. The proposed fourth-order filter was fabricated on GaAs substrate with dielectric thickness of 50 m and gold thickness of 1.2 mum. The fabricated fourth-order BPF shows a 3 dB bandwidth from 177 to 209 GHz frequency range with insertion loss of 6.5 dB, rejection of 38 dB and return loss better than 12 dB. It has a high resolution fractional bandwidth of 17%.     

A 0.4 ps-RMS-Jitter 1–3 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification

This paper presents the design and experimental results of a 0.4 ps rms jitter (integrated from 3 kHz to 300 MHz offset at 2.5 GHz) 1–3 GHz tunable ring-oscillator PLL for integrated clock multiplier applications. A new loop filter structure based on a sample-reset phase-to-voltage converter and a Gm-C filter decouples reference spur performance from charge-pump current matching and loop filter leakage, while enables phase error preamplification to lower PLL in-band noise without reducing VCO analog tuning range or increasing loop filter capacitor size. The ring-oscillator VCO features programmability of phase noise and power consumption at a given frequency. The PLL is implemented in a digital 0.13 $mu{hbox{m}}$ CMOS process using only 1.2 V devices, occupies 0.07 ${hbox{mm}}^{2}$ and consumes 23 mW excluding reference clock receiver for 2.5 GHz output at the lowest phase noise mode.      

A 30–100 GHz Wideband Sub-Harmonic Active Mixer in 90 nm CMOS Technology

This letter presents a 30–100 GHz wideband and compact fully integrated sub-harmonic Gilbert-cell mixer using 90 nm standard CMOS technology. The sub-harmonic pumped scheme with advantages of high port isolation and low local oscillation frequency operation is selected in millimeter-wave mixer design. A distributed transconductance stage and a high impedance compensation line are introduced to achieve the flatness of conversion gain over broad bandwidth. The CMOS sub-harmonic Gilbert-cell mixer exhibits ${-}{hbox{1.5}} pm {hbox{1.5}}$ dB measured conversion gain from 30 to 100 GHz with a compact chip size of 0.35 mm$^{2}$. The OP$_{1 {rm dB}}$ of the mixer is ${-}$ 10.4 dBm and ${-}$9.6 dBm at 77 and 94 GHz, respectively. To the best of our knowledge, the monolithic microwave integrated circuit is the first CMOS Gilbert-cell mixer operating up to 100 GHz.      

A 2–40 GHz Active Balun Using 0.13 $mu{rm m}$ CMOS Process

A 2 to 40 GHz broadband active balun using 0.13 $mu{rm m}$ CMOS technology is presented in this letter. Using two-stage differential amplified pairs, the active balun can achieve a wideband performance with the gain compensation technique. This active balun exhibits a measured small signal gain of ${0} pm{1}~{rm dB}$, with the amplitude imbalances below 0.5 dB and the phase differences of ${180} pm {10} ^{circ}$ from 2 to 40 GHz. The core active balun has a low power consumption of 40 mW, and a compact area of 0.8 mm $times,$ 0.7 mm. This proposed balun achieved the highest operation frequency, the widest bandwidth, and the smallest size among all the reported active baluns.      

Novel Composite Phase-Shifting Transmission-Line and Its Application in the Design of Antenna Array

A novel composite phase-shifting transmission line (TL) with designable characteristics is presented, which can be used to achieve arbitrary phase of the transmission coefficient at any required frequency with a certain length of the TL. An empirical formula is given of the relationship between the phase and physical length of the composite TL at a required frequency. A sample of 0$^{circ}$ phase-shifting TL is designed in details, and is verified by the full-wave simulation. At the required frequency of 5 GHz, the amplitude of ${rm S}_{21}$ is equal to $-0.23~{rm dB}$ with a phase of $-0.467^{circ}$. The electric length is only $0.212lambda_{0}$ , which has been decreased by 68.5% compared to the conventional microstrip line. Using the proposed composite TL, an antenna array is designed with two radiation patches excited by the novel series feed-line. The detailed procedure of such design is presented. The lowest reflection coefficient is exactly achieved at the required frequency of 5 GHz. The maximum radiation is obtained at $theta_{0}=0^{circ}$ , which indicates that the 0$^{circ}$ phase-shifting TL works very well. The sample is also fabricated and good agreements between simulation and measurement results are obtained.      

Design of a Beam Switching/Steering Butler Matrix for Phased Array System

A compact broadband 8-way Butler matrix integrated with tunable phase shifters is proposed to provide full beam switching/steering capability. The newly designed multilayer stripline Butler matrix exhibits an average insertion loss of 1.1 dB with amplitude variation less than $pm$2.2 dB and an average phase imbalance of less than 20.7$^{circ}$ from 1.6 GHz to 2.8 GHz. The circuit size is only $160times 100 {rm mm}^{2}$, which corresponds to an 85% size reduction compared with a comparable conventional microstrip 8-way Butler matrix. The stripline tunable phase shifter is designed based on the asymmetric reflection-type configuration, where a Chebyshev matching network is utilized to convert the port impedance from 50 $Omega$ to 25 $Omega$ so that a phase tuning range in excess of 120$^{circ}$ can be obtained from 1.6 GHz to 2.8 GHz. To demonstrate the beam switching/steering functionality, the proposed tunable Butler matrix is applied to a 1 $times$ 8 antenna array system. The measured radiation patterns show that the beam can be fully steered within a spatial range of 108 $^{circ}$.      

A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery

This paper presents a 40 Gb/s serial-link receiver including an adaptive equalizer and a CDR circuit. A parallel-path equalizing filter is used to compensate the high-frequency loss in copper cables. The adaptation is performed by only varying the gain in the high-pass path, which allows a single loop for proper control and completely removes the RC filters used for separately extracting the high- and low-frequency contents of the signal. A full-rate bang-bang phase detector with only five latches is proposed in the following CDR circuit. Minimizing the number of latches saves the power consumption and the area occupied by inductors. The performance is also improved by avoiding complicated routing of high-frequency signals. The receiver is able to recover 40 Gb/s data passing through a 4 m cable with 10 dB loss at 20 GHz. For an input PRBS of 2 $^{7}-$1, the recovered clock jitter is 0.3 ps$_{rm rms}$ and 4.3 ps$_{rm pp}$. The retimed data exhibits 500 mV $_{rm pp}$ output swing and 9.6 ps$_{rm pp}$ jitter with ${hbox{BER}}≪ 10^{-12}$ . Fabricated in 90 nm CMOS technology, the receiver consumes 115 mW , of which 58 mW is dissipated in the equalizer and 57 mW in the CDR.      

ALMA Band 1 Optics (35–50 GHz): Tolerance Analysis,Effect of Cryostat Infrared Filters and Cold Beam Measurements

The Atacama Large Millimeter/Sub-millimeter Array (ALMA) is currently the largest (sub-)mm wave telescope in the world and will be used for astronomical observations in all atmospheric windows from 35 to 950 GHz when completed. The ALMA band 1 (35–50 GHz) receiver will be used for the longest wavelength observations with ALMA. Because of the longer wavelength, the size of optics and waveguide components will be larger than for other ALMA bands. In addition, all components will be placed inside the ALMA cryostat in each antenna, which will impose severe mechanical constraints on the size and position of receiver optics components. Due to these constraints, the designs of the corrugated feed horn and lens optics are highly optimized to comply with the stringent ALMA optical requirements. In this paper, we perform several tolerance analyses to check the impact of fabrication errors in such an optimized design. Secondly, we analyze the effects of operating this optics inside the ALMA cryostat, in particular the effects of having the cryostat IR filters placed next to the band 1 feed horn aperture, with the consequent near-field effects. Finally, we report on beam measurements performed on the first three ALMA band 1 receivers inside test cryostats, which satisfy ALMA specifications. In these measurements, we can clearly observe the effects of fabrication tolerances and IR filter effects on prototype receiver performance.     

A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link

This paper presents a directly modulated, 60 GHz zero-IF transceiver architecture suitable for single-carrier, low-power, multi-gigabit wireless links in nanoscale CMOS technologies. This mm-wave front end architecture requires no upconversion of the baseband signals in the transmitter and no analog-to-digital conversion in the receiver, thus minimizing system complexity and power consumption. All circuit blocks are realized using sub-1.0 V topologies, that feature only a single high-frequency transistor between the supply and ground, and which are scalable to future 45 nm, 32 nm, and 22 nm CMOS nodes. The transceiver is fabricated in a 65 nm CMOS process with a digital back-end. It includes a receiver with 14.7 dB gain and 5.6 dB noise figure, a 60 GHz LO distribution tree, a 69 GHz static frequency divider, and a direct BPSK modulator operating over the 55–65 GHz band at data rates exceeding 6 Gb/s. With both the transmitter and the receiver turned on, the chip consumes 374 mW from 1.2 V which reduces to 232 mW for a 1.0 V supply. It occupies 1.28$,times,$0.81 mm$^{2}$. The transceiver and its building blocks were characterized over temperature up to 85$^{circ}$ C and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on slow, typical, and fast process splits. The transceiver architecture and performance were validated in a 1–6 Gb/s 2-meter wireless transmit-receive link over the 55–64 GHz range.      

A Low Loss High Isolation DC-60 GHz SPDT Traveling-Wave Switch With a Body Bias Technique in 90 nm CMOS Process

In this letter, a low loss high isolation broadband single-port double-throw (SPDT) traveling-wave switch using 90 nm CMOS technology is presented. A body bias technique is utilized to enhance the circuit performance of the switch, especially for the operation frequency above 30 GHz. The parasitic capacitance between the drain and source of the NMOS transistor can be further reduced using the negative body bias technique. Moreover, the insertion loss, the input 1 dB compression point (${rm P} _{{1}~{rm dB}}$), and the third-order intermodulation (IMD3) of the switch are all improved. With the technique, the switch demonstrates an insertion loss of 3 dB and an isolation of better than 48 dB from dc to 60 GHz. The chip size of the proposed switch is 0.68 $,times,$0.87 ${rm mm}^{2}$ with a core area of only 0.32$,times,$0.21 ${rm mm}^{2}$.      

A Fully Integrated 0.13- $mu$m CMOS 40-Gb/s Serial Link Transceiver

A fully integrated 40-Gb/s transceiver fabricated in a 0.13-$mu$m CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low ${rm f}_{rm T}$ of 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4$, times ,$2.9 mm$^{2}$ with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2$^{15}-1$ PRBS data is 1.85 ${rm ps}_{rm rms}$ over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 ${rm ps}_{rm rms}$ and the measured BER of the transceiver is less than $10^{- 14}$ .