Planar fully ion implanted InP power junction FET's

This letter reports on the fabrication and performance of planar all ion-implanted 1.0-µm gate length InP power junction field effect transistors (JFET's). The devices were fabricated utilizing n+ implantation, a AuZn/TiW/Au gate metallization, and an n+ drain ledge. At 4.5 GHz, the 300-µm gate width JFET's exhibited maximum insertion gains of up to 13 dB and scaled output powers as high as 1 W/mm with 3-dB gain.     

Integrated amplifiers using fully ion-implanted InP JFETs with hightransconductance

Monolithically integrated amplifiers have been fabricated using JFETs with a gate length of 1.5 μm and a maximum transconductance of 110 mS/mm, the highest ever reported for ion-implanted InP JFETs. The amplifiers utilized both a conventional direct-coupled design and a new symmetrical design. The conventional direct-coupled amplifier shows a maximum gain of 8 (18 dB) while the symmetrical amplifier design exhibits the same gain without DC offset regardless of the FET threshold voltage and the power supply voltage used     

Fully ion-implanted abrupt pn junction on semi-insulating InP

We report a fully ion-implanted pn junction using Si for n-implant and P/Be co-implant for a shallow p+ surface layer. C/V measurements indicate abrupt junction behaviour. Mesa diodes were fabricated and showed an ideality factor of two, small leakage current and avalanche breakdown at reverse bias greater than 40 V.     

DC characterization of fully ion-implanted p-n junctions intosemi-insulating InP

The forward and reverse characteristics of p⁺-n junctions made by Mg and Si implantation and rapid thermal annealing into Fe-doped semi-insulating InP are described. The effects of the Si dose for obtaining the n-type region, the use of P co-implantation for obtaining the p⁺ region, and the annealing time are studied. The dominant conduction mechanism at forward bias was found to be recombination in the space-charge region, with ideality factors of n=2 down to 198 K, and temperature dependence with an activation energy of 0.76 eV. The reverse characteristics presented junction breakdown at voltages around -20 V, and were accurately described by a thermally-activated trap-assisted tunneling mechanism. The energy of the corresponding trap, obtained by the fitting of the experimental characteristics, was 0.6 eV, and its origin was tentatively ascribed to the Fe deep acceptor present in semi-insulating InP     

Power gain and noise of InP and GaAs insulated gate microwave FETs

LPE GaAs and InP n-channel depletion mode insulated gate field effect transistors (MISFETs) having 4 μm gate lengths have been fabricated employing pyrolytic Si_xO_yN_z, pyrolytic SiO₂ and an anodic dielectric for gate insulation.The microwave power gain, noise figure, maximum output power and power-added efficiency were measured and compared to those parameters measured on GaAs Schottky barrier gate devices of identical geometry. The results show that, at least at the microwave frequencies measured, power gain and noise are essentially the same in the GaAs Schottky gate FET and anodic MISFET devices while the maximum output power of a typical InP MISFET was greater than that of a representative GaAs Schottky device.     

High-speed and high-power GaInAsP/InP junction field-effecttransistor with submicron gate

Depletion-mode GaInAsP/InP junction field-effect transistors have been fabricated on Fe-doped semi-insulating InP substrates using liquid-phase epitaxial growth techniques. The authors achieved transconductance of 24 mS (160 mS/mm), drain-source saturation current at an on gate bias of 486 mA/mm and current cutoff frequency of 18.8 GHz using a GaInAsP channel layer owing to the gate length reduction     

p+-AlInAs/InP junction FETs by selective molecular beamepitaxy

p⁺-AlInAs/InP junction field-effect transistors (FETs) have been fabricated in semi-insulating InP:Fe using ion implantation and a selective molecular-beam epitaxy (MBE) technique. Current-voltage measurements on 4.0-μm gate-length devices show a zero-gate-bias transconductance of 41 mS/mm, and RF measurements indicate a unity-power-gain frequency of 3.2 GHz. These results indicate that the selective growth method is a viable technique for fabricating high-frequency, high-power junction FETs in the InP-based materials system     

Fully ion-implanted InP JFET with buried p-layer

Implementation of a buried p-layer in a fully ion implanted InP JFET is discussed. Using Be coimplanted with Si, a sharp channel profile is obtained. The saturation current has been reduced, and the pinch-off characteristic has been improved, with a slight decrease in transconductance and cutoff frequency. The equivalent circuits for the JFET with and without the buried p-layer are compared     

Resistance associated with FET gate metallization

The resistance of the metallization of a FET gate stripe has the effect of placing a non-linear resistance R(I) in series with the gate junction. A simple means of calculating R(I) is developed, and a curve of the drop across R(1) at milliampere forward biases is given.     

Planar,ion-implanted bipolar devices in GaAs

Selected-area ion implantation using heavy metal masks to define the device geometry has been used to fabricate doubly implanted npn bipolar transistors and planar, isolated pn junction devices in GaAs. The bipolar transistors exhibited common-emitter current gains as high as 25. Collector-base breakdown voltages of 45 V were observed. The junction diodes (～200 um dia.) exhibited sub-nanoampere leakage currents at 15 V of reverse bias. Surface leakage appears to be the dominant mechanism responsible for the observed leakage currents. The diode forward current is limited by recomination in the space charge region.     

High-performance dual-gate carbon nanotube FETs with 40-nm gate length

We report on a high-performance back-gated carbon nanotube field-effect transistor (CNFET) with a peak transconductance of 12.5 /spl mu/S and a delay time per unit length of /spl tau//L=19 ps//spl mu/m. In order to minimize the parasitic capacitances and optimize the performance of scaled CNFETs, we have utilized a dual-gate design and have fabricated a 40-nm-gate CNFET possessing excellent subthreshold and output characteristics without exhibiting short-channel effects.     

Relationships between common source, common gate, and common drain FETs

This paper comprehensively analyzes the relationship between common source (CS), common gate (CG), and common drain (CD) field-effect transistors (FETs). The signal and noise parameters of the CG and CD configuration can be obtained directly by using a simple set of formulas from CS signal and noise parameters. All the relationships provide a bi-directional bridge for the transformation between CS, CG, and CD FETs. This technique is based on the combination of an equivalent-circuit model and conventional two-port network signal/noise correlation matrix technique. The derived relationships have universal validity, but they have been verified at 2/spl times/40 /spl mu/m gatewidth (number of gate fingers /spl times/ unit gatewidth) double-heterojunction /spl delta/-doped AlGaAs/InGaAs/GaAs pseudomorphic high electron-mobility transistor with 0.25-/spl mu/m gate length. Good agreement has been obtained between calculated and measured results.     

A vertical FET with self-aligned ion-implanted source and gate regions

A new self-aligned vertical channel JFET has been fabricated using ion-implantation and LOCOS techniques. This device required four photolithography processes. Fine patterning and accurate mask alignment are not required by this process. The electrical properties of this device are a voltage amplification factor of more than 5, a source-to-gate breakdown voltage of 50 V, and a drain-to-gate breakdown voltage of 140 V. It is possible to realize a larger voltage amplification factor, compared to the diffused vertical FET.     

Below 10 ps/gate operation with buried p-layer SAINT FETs

GaAs SAINT FETs with a p-layer buried under the active layer have achieved below 10 ps/gate (9.9 ps/gate) operation for the first time in semiconductor devices. The p-layer formed by Be+ implantation is completely depleted by the built-in potential. It has successfully alleviated the short channel effects without increasing parastic capacitance.     

InGaAs avalanche photodiode with InP p-n junction

A new InGaAs avalanche photodiode structure that has an InGaAs light absorption region and InP avalanche multiplying region is proposed. A dark-current density of 2.2 × 10?3 A/cm2 at 90% of breakdown voltage and a multiplication factor of 45 were obtained for the new structure diode fabricated from a liquid-phase epitaxially grown wafer.     

Planar InP avalanche photodiode with Zn-diffused guard ring

A guard ring structure with a p+-n?-n junction formed by Zn diffusion at 450°C gave a high gain planar InP avalanche photodiode. A maximum multiplication factor of more than 50 was obtained uniformly within the photosensitive area without edge breakdown.     

Hydrogen sensitivity of InP HEMTs with WSiN-based gate stack

We have experimentally investigated the hydrogen sensitivity of InP high-electron mobility transistors (HEMTs) with a WSiN-Ti-Pt-Au gate stack. We have found that exposure to hydrogen produces a shift in the threshold voltage of these devices that is one order of magnitude smaller than published data on conventional Ti-Pt-Au gate HEMTs. We have studied this markedly improved reliability through a set of quasi-two-dimensional mechanical and electrostatic simulations. These showed that there are two main causes for the improvement of the hydrogen sensitivity. First, the separation of the Ti-layer from the semiconductor by a thick WSiN layer significantly reduces the stress in the heterostructure underneath the gate. Additionally, the relatively thinner heterostructure used in this study and the presence of an InP etch-stop layer with a small piezoelectric constant underneath the gate reduces the amount of threshold voltage shift that is caused by the mechanical stress.     

Planar filter design with fully controllable second passband

New designs of the dual-band filter realized by distributed circuits are studied in this paper. Series and parallel open stubs are used as the resonators to fulfil the dual-band characteristics. Two dual-band inverters are proposed, which can be easily merged with adjacent resonators to reduce the circuit size. All the theoretical analysis and design procedures are discussed in detail and have been successfully verified by experiment results.     

Monolithic integration of fully ion-implanted lateral GaInAs pin detector/InP JFET amplifier for 1.3-1.55 mu m optical receivers

An optical receiver front-end consisting of a lateral interdigitated GaInAs pin detector integrated with an InP JFET amplifier has been fabricated. This lateral detector structure simplifies the GaInAs material growth requirement to a single layer and provides low capacitance. A quasiplanar approach has been developed in conjunction with a two-level metallisation interconnect scheme. An optical sensitivity of -29 dBm was measured at 560 Mbit/s and 1.3 mu m wavelength.<>     

Below 20 ps/gate operation with GaAs SAINT FETs at room temperature

Room-temperature ring oscillation at 19.6 ps/gate has been accomplished with SAINT FETs using bulk GaAs and implantation. These results have been obtained along with extrinsic resistance reduction and capacitance reduction by taking full advantage of the n+-gate spacing controllability.