Heavy oxynitridation technology for forming highly reliable flash-type EEPROM tunnel oxide films

For the first time, it is demonstrated that in flash-type EEPROMs, the endurance properties are dramatically improved by heavy oxynitridation (RTONO) of the tunnel oxide. The layer composition evaluated by SIMS measurement indicates that large amounts of N atoms (>10/sup 20/ atom/cm/sup 3/) pile up at the SiO/sub 2/-Si interface, and are distributed in the bulk SiO/sub 2/. In addition, the RTONO film reduces the number of hydrogen atoms, which are the origin of electron traps. This oxynitridation causes a decrease of both electron and hole traps in the tunnel oxide, resulting in an improvement of the threshold voltage narrowing.<>     

Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injection

The lateral profile of trapped charge in a silicon-oxide-nitride-oxide-silicon (SONOS) electrically erasable programmable read-only memory programmed using channel-hot-electron injection is determined using current-voltage (I/sub D/-V/sub G/) measurements along with two-dimensional device simulations and is verified using gate-induced-drain-leakage measurements, charge-pumping (CP) measurements, and Monte Carlo simulations. An iterative procedure is used to match simulated I/sub D/-V/sub G/ characteristics with experimental I/sub D/-V/sub G/ characteristics at different stages of programming, by sequentially increasing the trapped electron charge in simulations. Fresh cells are found to contain a high laterally nonuniform trapped charge, which (along with large electron injection during the program) make the conventional CP techniques inadequate for extracting the charge profile. This charge results in a nonmonotonous variation of threshold and flat-band voltages along the channel and makes it impossible to simultaneously determine interface and trapped charge profiles using CP alone. The CP technique is modified for application to SONOS cells and is used to verify the charge profile obtained using I/sub D/-V/sub G/ and to estimate the interface degradation. This paper enhances the study presented in our earlier work.     

Determination of trapped oxide charge in flash EPROMs and MOSFETswith thin oxides

A technique for determining the sign and the effective density of the trapped oxide charge near the junction transition region, based on the measurement of the gate-induced drain leakage (GIDL) current, is used to investigate the hot-carrier effects resulting from the erase operation and bit-line stress in flash EPROM devices. While the trapped oxide charge depends on the stress conditions, it has been found that a significant amount of hole trapping is likely when a sufficiently large potential difference exists between the gate and junction for either an abrupt or graded junction     

High performance scaled flash-type EEPROMs fabricated by in situ multiple rapid thermal processing

Flash-type EEPROMs were fabricated for the first time by in situ multiple rapid thermal processing (RTP) modules. In the paper, rapid thermal oxynitridation tunnel oxide (RTONO) formation followed by in situ arsenic (As)-doped floating gate polysilicon growth by rapid thermal chemical vapour deposition (RTCVD) were introduced. The flash cell indicates only 20% narrowing of the V/sub t/ window after 5*10/sup 4/ program/erase cycle stress. Moreover, there is a higher breakdown field of the ONO film on the floating-gate polysilicon film owing to extremely flat poly-Si surface. Thus, the in situ multiple RTP technology is the key for future flash memory fabrication processes.<>     

Peculiarities of electron tunnel injection to the drain of EEPROMs

A specific time-resolved dynamic current measurement procedure is used to characterize high-field electron tunnel injection to the drain of EEPROMs. This allows the direct observation of a transient regime eventually occurring in the case of moderately doped drain. Another peculiarity is also evidenced, namely a stationary regime where measured current is far higher than anticipated by simulation. This is attributed to a non-equilibrium charge versus band-bending in the drain which is controlled by electron–hole pairs subsequent to impact ionization of electrons tunnelling from the gate.     

Hot electrons in MOS transistors: Lateral distribution of the trapped oxide charge

The spatial distribution (along the channel) of the oxide-trapped charge induced by hot electron injection in MOS transistors biased in saturation, is studied by means of two-dimensional device simulators. It is shown that hot electron trapping leads to a charge almost uniformly distributed over the region included between the points of channel pinch-off and zero transversal component of the surface electric field. A simplified analytic expression for the drain current in the triode operating region of the HE modified transistor is also given and found to be in reasonable agreement with experimental curves.     

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

A two-dimensional analytical model of double-gate(DG) tunneling field-effect transistors(TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile, the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate, and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.     

Determination of the spatial variation of interface trapped charge using short-channel MOSFET's

Previous measurements of interface trapped charge (ITC) by charge pumping used long-channel metal gate transistors. In this paper charge pumping is extended to short-channel Self-aligned polysilicon gate transistors and used to determine the spatial variation of ITC on wafers. Only the MOSFET gate area and a pulse frequency are required to calculate ITC density from the charge pumping current. In previous work, with long-channel devices, it appears that some investigators used the design dimension of metal gate devices and others used the metallurgical channel length of the transistors to calculate gate area. Two-dimensional simulation of the charge pumping measurement showed that, for a sufficient applied pulse height voltage, the correct area is obtained if the polysilicon gate length and width asmeasured are used. When the process-induced variation of the polysilicon gate length is included in the measurement analysis, no systematic variation of ITC is observed across 5 cm wafers. The charge pumping measurement technique on short-channel MOSFET's can be used to resolve the spatial variation of ITC if the area variations are correctly handled. The measurement of ITC is linear with frequency from 1 kHz to 1 MHz, indicating that the emission time constant of the fast states measured using this method is ≤10^-6s. A variation of ITC with channel lengths is also observed. This variation could not be detected using large area devices such as capacitors, but will have important consequences for short-channel MOSFET's.     

Monitoring trapped charge generation for gate oxide under stress[MOS capacitors]

A measurement method to extract the respective quantities and centroids of positive and negative trapped charges, i.e., Q_p and Q_n, generated by the negative current stress for gate oxides is proposed and demonstrated. The method is based on neutralization of and by a low positive current stress to differentiate the effects of Q_p and Q_n. From the extracted quantities and centroids of Q_p and Q_n of negatively stressed oxides, it was found that Q_p and Q_n are generated near the oxide/substrate interface and Q_p is initially much larger than Q_n. After the continuous stressing, Q_p saturates and moves closer to the interface, but Q_n keeps increasing and moves away from the interface, especially for those oxides after the post-poly anneal (PPA) treatment. Q_p is very unstable and easily neutralized, either by a small stress of opposite polarity or the same polarity. For the latter, Q_p is mainly dependent on the level of the final stressing field     

Optical generation of free charge carriers in thin films of tin oxide

The methods of infrared absorption spectroscopy and Raman spectroscopy are used to study nanocrystalline SnO _x films (1 ≤ x ≤ 2) prepared by thermal oxidation of metallic tin layers. A monotonic decrease in the transmittance of films in the infrared region has been observed as a result of exposure of the films to light with the wavelength of 380 nm at room temperature. The effect is at a maximum for the samples with x ≈ 2 and is observed for ∼10 min after switching off of illumination. The mentioned variations in optical properties, similarly to those observed in the case of heating of the samples in the dark, are accounted for by an increase in the concentration of free charge carriers (electrons) in nanocrystals of tin dioxide. The data of infrared spectroscopy and the Drude model are used to calculate the concentrations of photogenerated charge carriers (∼10¹⁹ cm⁻³); variations in these concentrations in the course of illumination and after switching off of illumination are determined. Mechanisms of observed photogeneration of charge carriers in SnO _x films and possible applications of this effect to gas sensors are discussed.     

A new method to extract gate coupling ratio and oxide trapped charge in flash memory cell

A new method to obtain the gate coupling ratio (α_g) and oxide trapped charge (Q_ox) as a result of cycling in flash memory cells is described here. Three cells with an equivalent physical structure but different erase characteristics are measured. The threshold changes versus erase times are fitted to the charge removal rate calculated based on Fowler-Nordheim (FN) tunneling and the capacitive relations among all nodes. The extracted α_g is independent of technologies and this method is particular useful when the profile of the floating gate is not traditionally rectangular owing to advanced processes such as trapezoidal poly etch or a poly-spacer addition on the floating gate sidewall. The Q_ox can also be determined once α_g is extracted.     

Endurance of EEPROMs with On-Chip Error Correction

This paper presents an endurance model for EEPROMs utilizing an on-chip error-correction code (ECC). This is necessary to determine the effect that ECC schemes have upon endurance (and therefore, reliability) of EEPROMs. EEPROM technology is briefly discussed.     

陷阱俘获存储器中电荷积累过程对保持特性的影响

本文通过数值模拟的方法对陷阱俘获存储器单元在多次擦写过程中的电荷积累过程进行了分析。由于多次擦写后陷阱电荷的积累,电荷之间的复合过程成为一个重要的问题。分析结果显示擦写过程中积累的空穴会对存储器的保持特性产生影响,同时在分析器件保持特性的时候电荷之间的复合机制必须加以考虑。     

A method for separating the effects of interface from border and oxide trapped charge densities in mos transistors

This paper presents a procedure for a more accurate separation of interface trap effects in the presence of large border trap densities after irradiation of MOS devices. It is based on the standard subthreshold technique, but a special measurement procedure is applied which eliminates the drifts produced by border traps via the tunneling effect. The procedure is demonstrated on pMOS dosimetric transistors, and it is shown that it gives different and, we claim, better estimates of interface trap density than standard techniques.     

Effect of trapped charge accumulation on the retention of charge trapping memory

The accumulation process of trapped charges in a TANOS cell during P/E cycling is investigated via numerical simulation.The recombination process between trapped charges is an important issue on the retention of charge trapping memory.Our results show that accumulated trapped holes during P/E cycling can have an influence on retention,and the recombination mechanism between trapped charges should be taken into account when evaluating the retention capability of TANOS.     

Thickness determination of ultrathin oxide films and its application in magnetic tunnel junctions

In this study we propose a method for utilizing x-ray photoelectron spectroscopy (XPS), a surface sensitive technique, coupled with a wedge-shaped sample to determine the thickness of an ultrathin aluminum oxide tunnel barrier layer (∼2 nm) in a magnetic tunnel junction (MTJ). The uncertainty of the measured thickness is analyzed and the factors affecting the accuracy of this measurement are discussed as well as the advantages over the use of high-resolution transmission electron microscopy. Using this approach, we were able to quickly optimize the thickness of an aluminum oxide layer in a fabricated MTJ, yielding a high magnetoresistance ratio. In addition to XPS, one can also use Auger electron spectroscopy to determine the thickness of the oxidized tunnel barrier layer. This method can also be applied to other tunnel barrier materials such as the nitrides.     

一种应用于纳米尺度器件陷阱电荷表征的新型改进电荷泵方法

随着器件特征尺寸的缩小,热载流子带来的器件蜕化效应越来越严重。电荷泵方法可用于表征陷阱电荷的分布。但由于局部阈值电压窄峰的影响,传统电荷泵法在测试陷阱电荷分布时存在误差。本文提出了一种改进型电荷泵测试方法,可用于精确提取纳米尺度器件中陷阱电荷的横向分布。 本文采用0.12微米的SONOS器件来验证这一方法的有效性。通过编程控制,使SONOS器件形成大约50纳米的阈值电压窄峰。采用新方法测试得到的陷阱电荷分布与测试得到的阈值电压有较好的一致性。     

A novel modified charge pumping method for trapped charge characterization in nanometer-scale devices

A new modified method based on the charge pumping technique is proposed and adopted to extract the lateral profiles of oxide charges in an advanced MOSFET.A 0.12μm SONOS device with 50 nm threshold voltage peak is designed and utilized to demonstrate the proposed method.The trapped charge distribution with a narrow peak can be precisely characterized with this method,which shows good consistency with the measured threshold voltage.     

Electrical properties of heavily doped polycrystallinesilicon-germanium films

The electrical properties of polycrystalline silicon-germanium (poly-Si_1-xGe_x) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented. The resistivity of heavily doped p-type (P⁺) poly-Si_1-x Ge_x is much lower than that of comparably doped poly-Si, because higher levels of boron activation and higher hole mobilities are achieved in poly-Si_1-xGe_x. The resistivity of heavily doped n-type (N⁺) poly-S_1-xGe_x is similar to that of comparably doped poly-Si for x<0.45; however, it is considerably higher for larger Ge mole fractions due to significant reductions in phosphorus activation. Lower temperatures (~500°C), as well as lower implant doses, are sufficient to achieve low resistivities in boron-implanted poly-Si_1-xGe_x films, compared to poly-Si films. The work function of P⁺ poly-Si_1-xGe_x decreases significantly (by up to ~0.4 Volts), whereas the work function of N⁺ poly-Si_1-xGe_x decreases only slightly, as Ge content is increased. Estimates of the energy bandgap of poly-Si_1-xGe_x show a reduction (relative to the bandgap of poly-Si) similar to that observed for unstrained single-crystalline Si_1-xGe_x for a 26% Ge film, and a reduction closer to that observed for strained single-crystalline Si _1-xGe_x for a 56% Ge film. The electrical properties of poly-Si_1-xGe_x make it a potentially favorable alternative to poly-Si for P⁺ gate-material applications in metal-oxide-semiconductor technologies and also for p-channel thin-film transistor applications     

On the characterization of the trapped charge in FG-CMOS inverters

In this work, an experimental comparison between measured FG CMOS inverters using the quasi-floating gate (QFG) and layout-based (L-b) techniques for charge removal in the Floating-gate (FG) and simulations through PSpice is presented. The experiment was developed through the measurements of 40 different IC’s with a total of 200 FG and QFG CMOS inverters characterized on AMI C5FN 0.5 μm technology. The data obtained shows that the layout-based technique reduces the initial charge present at the FG, but presents a very small residual charge. Nevertheless, the offset associated to the charge follows a normal distribution and is predictable. Comparison between measured QFG inverters and simulations shows that the high resistance parasitic diode must be modeled accurately for a proper simulation.