Adaptive dynamic programming

Unlike the many soft computing applications where it suffices to achieve a "good approximation most of the time," a control system must be stable all of the time. As such, if one desires to learn a control law in real-time, a fusion of soft computing techniques to learn the appropriate control law with hard computing techniques to maintain the stability constraint and guarantee convergence is required. The objective of the paper is to describe an adaptive dynamic programming algorithm (ADPA) which fuses soft computing techniques to learn the optimal cost (or return) functional for a stabilizable nonlinear system with unknown dynamics and hard computing techniques to verify the stability and convergence of the algorithm. Specifically, the algorithm is initialized with a (stabilizing) cost functional and the system is run with the corresponding control law (defined by the Hamilton-Jacobi-Bellman equation), with the resultant state trajectories used to update the cost functional in a soft computing mode. Hard computing techniques are then used to show that this process is globally convergent with stepwise stability to the optimal cost functional/control law pair for an (unknown) input affine system with an input quadratic performance measure (modulo the appropriate technical conditions). Three specific implementations of the ADPA are developed for 1) the linear case, 2) for the nonlinear case using a locally quadratic approximation to the cost functional, and 3) the nonlinear case using a radial basis function approximation of the cost functional; illustrated by applications to flight control.     

Dedicated Circuits for the Generation of Windows in Image Processing Architectures

A formal methodology for the design of window generator circuits is proposed. The methodology focuses on the design of optimised dedicated structures and allows to exploit modularity for evaluating design alternatives and cost/performances trade-offs. The discussed architectural model is based on a suitable mathematical representation (called transformation) of a generic window generator circuit and allows both a global and a modular design style. Such features are used to design a library of universal functional blocks allowing to synthesise any type of window generator circuit. The architectural model is evaluated by implementing the functional blocks and by synthesising in VLSI technologies a set of representative window generator circuits. The trade-off between cost and performance of the synthesised window generator circuits is presented and discussed.     

Suboptimal linear control of the linear regulator using incomplete state feedback

A simple method is outlined for the design of the optimal linear partial-state feedback control for the time-invariant state regulator assuming that the initial-state mean and variance are known. The cost functional minimised is average, over all initial states, of the usual integral quadratic cost. The method is compared with that recently suggested by Dabke.     

Disturbance Attenuation in Hyperbolic 2D-systems

We consider disturbed linear 2D-systems of Fornasini–Marchesini type in the continuous time case. These systems are also named Goursat-type systems. Conditions for unique solvability of the disturbed optimal control problem with a quadratic cost functional are obtained. The disturbed or worst case optimal control guarantees to minimize the cost functional for any unknown disturbance input. In a second part then we consider a disturbance attenuation by boundary controls, i.e., by using the Goursat-data as control functions. In the 2D-case this results in two control functions acting independently on the system. We study a cooperative and a non-cooperative situation. In the cooperative situation we again obtain a disturbed optimal control problem and get conditions for existence and uniqueness of such a disturbed optimal control problem. If the action of the agents is non-cooperative we assume that it is agreed that they act on an open-loop Nash/worst-case equilibrium strategy. Sufficient conditions for the existence of such an equilibrium are obtained. Published online: April 2006     

Statistical Design of Low Power Square-Law CMOS Cells for High Yield

A robust design of low voltage low power square law CMOS composite cells using statistical VLSI design techniques is presented. Since random device/process variations do not scale down with feature size or supply voltage, the statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. The Response Surface Methodology and Design of Experiment techniques were used as statistical techniques. This article shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.     

A peripheral-oriented microcomputer system

The inherent low cost afforded by MOS/LSI technology has been widely exploited in the functional areas of CPU's, ROM's, and RAM's. Much less attention has been given to I/O and peripheral controller applications. In many microcomputer systems, as in conventional computer systems, the cost of I/O and peripheral control may far overshadow CPU costs. This paper describes an integrated-systems design which makes full use of MOS/LSI capabilities for all commonsystems functions. In this approach, intelligence is distributed throughout the system instead of being concentrated in the CPU. A single-chip floppy-disk controller is described to illustrate the capability of MOS/LSI in peripheral control.     

Optimum design method of optoelectronic devices using simulatedannealing

A design methodology for optimizing optoelectronic functional devices is described. The introduction of cost function for electrical and optical device characteristics enables automatic optimization by simulated annealing. The optimum design of AlGaAs/GaAs pnpn differential optical switches in consideration of light emission efficiency, light sensitivity, and switching voltage is successfully demonstrated     

氧化石墨烯修饰的功能复合纸用于高效去除水中重金属Pb(Ⅱ)的研究

以氧化石墨烯修饰的功能复合纸为吸附材料,研究其对水中重金属Pb(Ⅱ)离子的吸附能力,探讨了吸附剂的用量和初始浓度等净化条件对吸附效果的影响。结果表明:氧化石墨烯修饰的功能复合纸的结构平整、化学性质稳定,易分离;功能复合纸对Pb(Ⅱ)离子有良好的吸附能力,且吸附效果全部归功于氧化石墨烯的作用;功能复合纸上负载的氧化石墨烯用量增加反而降低单位质量氧化石墨烯对Pb(Ⅱ)的吸附量,在所研究的净化条件中,吸附量跨度为90 mg/g^500 mg/g;随着Pb(Ⅱ)初始浓度的增加,功能复合纸对Pb(Ⅱ)的吸附效果明显提升,当Pb(Ⅱ)离子溶液的初始浓度为350 mg/L时,吸附效果最佳。吸附反应动力学较好的符合伪二阶动力学模型,即吸附过程受化学作用主导,氧化石墨烯表面的含氧官能团在吸附过程中起到重要作用。功能复合纸在吸附饱和后,易于与水体分离,避免二次污染现象。     

基于遗传算法的某火控系统备份功能板优化模型

通过简要分析某火控系统的维修方式,建立了备份功能板费用与此火控系统效能的函数关系。根据实际情况,建立了在备份功能板费用一定的约束条件下火控系统的功能板(印制版)随机备件优化模型,结合遗传算法解优化问题的特点,将遗传算法引入到求解备件优化问题中来,有效地解决了这一复杂的备件优化问题,保证了此火控系统具有较高的可用度。     

A computationally efficient iterative solution of themultidestination optimal dynamic routing problem

The dynamic routing problem for multiple destination networks is considered. The minimum time rather than total delay cost functional is employed. The problem is solved through an iterative link-by-link optimization. Each link capacity is optimally partitioned by examining the upper bounds for the evacuation time imposed through different capacity allocations for each origin/destination pair traffic. The computational complexity per iteration is polynomial in the number of network nodes. This is due to the examination of origin/destination pairs rather then destinations alone as in previous work where a similar approach led to exponential complexity. Sufficient conditions for the convergence of the iterative algorithm to the optimum are given. If these are not satisfied supplementary steps are described which conduct the algorithm to the desired solution. These involve exponential computational complexity     

基于dsPIC33E的电动汽车充电机的研究与设计

本文设计了一种适合于混合动力汽车充电的充电系统,输入为单相交流市电,采用AC/DC和DC/DC相结合的拓扑结构以满足相应的国家标准和充电机的功能需求,利用低成本控制器dsPIC33E进行控制。在对上述主电路拓扑的工作原理进行分析的基础上,给出了部分关键参数的设计方法,并分别设计了前后级电路的控制策略。为了防止在后级DC/DC电路输出模式切换时引起振荡而设计了一种切换方法。最后在理论分析的基础上进行了仿真和实验研究,仿真和实验结果验证了本文所设计的充电机的可行性。     

A new optimization method for antenna design

The authors consider the class of conformal antennas consisting of bounded smooth closed curves in two dimensions and determine the surface field which maximizes power radiated in angular sector. The problem is cast as one of optimal control with the control set consisting of the surface current, constrained to have energy bounded by some constant, and the cost functional is taken to be the far field power radiated in an angular sector. A constructive algorithm is presented for approximating both the optimal value of the cost functional and the surface current which produce this optimal value. Bothte andtm polarizations are considered.     

IBPU:一种面向通用处理器架构的比特置换功能单元

本文利用Inverse Butterfly网络拓扑结构的自路由特性,并结合分治策略,提出了一种能够硬件高速实现任意比特置的换选路算法.利用该算法能够在O（lgN）条指令内完成N-bit任意静态置换操作,在O（lg²N）条指令内完成N-bit任意动态置换操作.在此基础上,本文构造了一种新型比特置换单元-Permutation Unit based on Inverse Butterfly,IBPU.并将它在SMIC 65nm工艺下进行了逻辑综合,结果表明：与以往研究成果相比,本文提出的IBPU资源消耗降低了约32%,延迟降低了近30%.当完成静态置换操作时,其功能单元所消耗的代价最小,不超过以往设计的60%;当完成动态置换操作时,虽然消耗的代价较大,但其随置换位宽N的增加涨幅较小,因此具有较高的稳定性,其综合性能优势明显.     

Low-cost direct chip attach: comparison of SMD compatible FCsoldering with anisotropically conductive adhesive FC bonding

Small modules on the basis of laminate substrates are often used as a functional subunit in electronic applications. Currently most of them are made by chip and wire technique as one kind of bare chip assembly to fulfill the requirements of size reduction. Low cost flip-chip technology is one of the most promising approaches for further cost and size reduction. In this paper a special car radio submodule is chosen for exemplification. We compare a SMD compatible FC soldering process using eutectic solder bumps and underfilling with an anisotropically conductive adhesive (ACA) FC bonding process using tape or paste materials. FC Soldering: For FC soldering an electroless, maskless Ni/Au plating for under bump metallization (UBM) was chosen. The solder deposition itself is done by stencil printing whereas other cost efficient deposition techniques in the market have been observed. The FC assembly is integrated into a standard SMD line. Different underfill methods for quick underfilling are shown and failure mechanisms and lifetime predictions of assembled flip chips are demonstrated. ACA-FC Bonding: For this process electroless Ni/Au bumping is used as well. An assembly process for ACAs using a semiautomatic FC bonder is developed. In order to reduce the time for mounting the ACA has been precured. The aspects of different process flows including ACA deposition techniques, tape and paste adhesives and filler materials are discussed. The influence of high current, climate, and thermal cycling on the contact resistance and the low frequency noise spectrum is shown. In summarizing this work we describe the benefits and disadvantages of both techniques and discuss the potential for further developments and applications     

An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge

Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.      

High-level synthesis of recoverable VLSI microarchitectures

Two algorithms that combine the operations of scheduling and recovery-point insertion for high-level synthesis of recoverable microarchitectures are presented. The first uses a prioritized cost function in which functional unit (FU) cost is minimized first and register cost second. The second algorithm minimizes a weighted sum of FU and register costs. Both algorithms are optimal according to their respective cost functions and require less than 10 min of central processing unit (CPU) time on widely used high-level synthesis benchmarks. The best previous result reported several hours of CPU time for some of the same benchmarks on a computer of similar computational power     

A high performance low power 2048-bit memory chip in MOSFET technology and its application

A static 2048-bit read/wire memory chip for main stores is described. It uses a modified 6-device memory cell in an n-channel MOSFET technology. To exploit the potential of the given MOSFET technology with respect to the cost/performance ratio and the power-delay product, special provisions are taken. The power is kept low by the gate driver concept as well as by clocked peripheral circuits. High performance is achieved with fast peripheral circuits, the delayed chip select concept, and a bipolar sense amplifier which also supplies the bit-line restore voltage. Circuits are presented which successfully utilize the on-chip tracking to reduce the impact of device parameter tolerances on worst case power and performance. It is shown how the memory chip is packaged on modules, cards, and boards to build up functional memory units.     

A Framework for High Level Estimations of Signal Processing VLSI Implementations

This paper deals with the presentation of a framework for the rapid prototyping of Digital Signal Processing applications. The BSS framework enables both synthesis of dedicated VLSI circuits and cost, performance estimation. The latter can be used at different accuracy levels and can help the designer in selecting a proper algorithm in order to improve the global performance of its implementation. The cost estimation takes into account both the processing unit, including operators, registers, interconnections, and memory units. The implemented estimation techniques are presented and include functional unit number bound calculation, probabilistic cost estimation of processing unit components, and memory unit area evaluation. We demonstrate, on a real application, that cost/signal processing quality trade-offs can be achieved while changing the type of algorithm and the number of filter taps for a given algorithm specification.     

基于AVR单片机大容量数据采集系统的设计

高速嵌入式AVR单片机广泛应用于数据采集控制系统中,但由于自身存储容量过小而不能尽其所能,外扩F lash芯片很好地解决了存储容量上的瓶颈,在提高单片机性能的同时大大降低了系统成本。基于此设计了5路A/D采集电路,同时介绍了各个芯片的特点、功能结构,并在此基础上给出了它们之间的硬件接口设计及程序设计流程。     

Finite-memory problems and algorithms

A formulation of finite-memory information processing problems is presented. The total state space of the system, including the "memory" of the source and processor, is assumed to be finite. A cost functional is specified over the trajectories of the system and a variational approach is used to minimize cost. There results a two-point boundary value problem and an associated improvement algorithm. Special attention is given to two types of cost functionals: finite-time problems, and time-average problems over an infinite time interval. Several examples are included.