低温烧结CuO-V_2O_5-Bi_2O_3掺杂Zn_3Nb_2O_8陶瓷的微波介电性能

研究了CuO–V2O5–Bi2O3作为烧结助剂对Zn3Nb2O8陶瓷的烧结特性、微观结构、相结构及微波介电性能的影响。CuO–V2O5–Bi2O3复合掺杂可以将Zn3Nb2O8陶瓷的烧结温度从1150℃降到900℃。在900℃烧结4h的Zn3Nb2O8–0.25%(质量分数,下同)CuO–1.5%V2O5–1.5%Bi2O3陶瓷的密度达到了理论密度的98.1%,相对介电常数为18.8,品质因数与谐振频率之积为39442GHz。该体系的介电性能和陶瓷的致密度与烧结助剂的含量及烧结温度密切相关,陶瓷的致密度和相对介电常数随CuO–V2O5–Bi2O3烧结助剂含量的增加而增加,同样陶瓷的致密度和相对介电常数也随烧结温度的升高而提高。     

B2O3掺杂对α-CaSiO3/Al2O3陶瓷低温烧结及微波介电性能的影响

通过传统固相法制备了α-CaSiO3/Al2O3-B2O3微波介质陶瓷,研究了不同B2 O3添加量对α-CaSiO3/Al2O3陶瓷烧结特性、相组成及微波介电性能的影响,通过XRD、SEM和网络分析仪对其相结构、微观形貌和微波介电性能进行了表征.结果表明:B2 O3的添加使陶瓷的烧结温度从1375℃降低到了1100℃,并使主晶相由α-CaSiO3相变为β-CaSiO3相;当B2 O3的添加量为3wt%时,在1100℃烧结2 h可获得最佳微波介电性能:εr=6.21,Q×f=30471 GHz,τf=-34.58 ppm/℃.     

低温烧结Mg4Nb2O9微波介质陶瓷

研究了V2O5对Mg4Nb2O9陶瓷的烧结温度、相结构和微波介电性能的影响.结果表明,添加1％～8％的V2O5,能使该陶瓷的烧结温度降低到1000～1050℃而对其微波介电性能的影响很小,材料的主晶相为有序型刚玉结构的Mg4 Nb2O9,存在Mg4Nb2O6和Mg5Nb4O15杂相而没有检测到V2O5的存在.陶瓷的密度对微波介电性能起着决定性作用,介电常数e1与密度成线性关系(在99.99％的置信限内,其相关系数为0.98252),Q·f值与密度的关系较复杂.添加1％的v2O5,将Mg4Nb2O9陶瓷的烧结温度降低到了1050℃,得到了εr=12.72,Q·f=151040GHz的优异性能.     

CuO和V2O5掺杂对ZnNb2O6陶瓷介电性能的影响

采用传统的固相反应法制备了CuO和V2O5掺杂的ZnNb2O6介质陶瓷.通过X射线衍射,扫描电镜以及电感-电容-电阻测试仪等测试手段对其烧结特性,晶体结构,微观形貌和介电性能进行研究.结果表明:CuO和V2O5掺杂能降低ZnNb2O6陶瓷的烧结温度,影响相结构,改变微观形貌并优化介电性能.掺杂质量分数为0.25%CuO和0.25%V2O5的ZnNb2O6陶瓷样品在1 025℃烧结后,在100 MHz下具有较好的综合介电性能:介电常数εr=35,介电损耗tanδ=0.000 21,频率温度系数τf=-44.41×10-6/℃.     

Al_2O_3添加量对CBS/Al_2O_3复相陶瓷结构与性能的影响

采用流延法制备CBS/Al2O3复相陶瓷。运用FTIR、XRD、SEM和EDS等分析测试手段研究了Al2O3添加量对CBS/Al2O3复相陶瓷微观结构和介电性能的影响。结果表明:随着α-Al2O3添加量的增加,钙长石相的形成抑制了石英相和硅灰石相的生长,试样的烧结温度和致密度明显提高,烧结温度范围扩大。但Al2O3添加量大于48%时,玻璃液相不足以充分润湿陶瓷相,导致体系致密度下降。Al2O3添加量为48%的复相陶瓷850℃烧结,密度ρ=3.11 g·cm-3,10 MHz频率下,介电常数εr=7.95,介电损耗tanδ=1.1×10-3,能够与金浆低温共烧。     

烧结温度对PCrNi-4压电陶瓷性能的影响

采用传统固相烧结法制备Pb0.94Sr0.06（Zr0.53Ti0.47）O3＋（Ni2O3＋Cr2O3）0.1wt%＋x wt%CeO2（简称PCrNi-4）压电陶瓷,其中x取值为0,0.1,0.3和0.5,研究了烧结温度对陶瓷样品的相结构、显微结构、压电及介电性能。结果标明：所有样品相结构均为三方相与四方向共存。当烧结温度为1280℃,CeO2掺杂量为0.3 wt%时,陶瓷的晶粒大小均匀,致密性良好,具有良好的压电及介电性能（d33=375 pC/N,Kp=0.70115,εT33=1400,tgδ=0.00238）。     

流延成型法制备Mn掺杂Ba_(0.6)Sr_(0.4)TiO_3/MgO陶瓷及其介电性能

用流延成型法制备Mn掺杂钛酸锶钡(BaxSr1-xTiO3,BST)/MgO复相陶瓷厚膜,介绍从制粉、流延浆料制备到厚膜的脱脂及烧结的整个工艺流程。通过差热-热重测试曲线分析Mn掺杂BST/MgO流延膜的脱脂特性,制定膜片的脱脂工艺。用扫描电镜观察不同温度烧结样品的微观结构,确定最佳厚膜烧结工艺,在1320℃和1350℃烧结的陶瓷厚膜样品的相对密度达到96.1%。分析研究不同温度烧结陶瓷厚膜的介电性能的结果表明:1350℃烧结样品的室温相对介电常数为108,介电损耗低于0.002,Curie温度在-70℃左右,介电常数可调率为25.15%。     

BaCu(B_2O_5)掺杂对0.4CaTiO_3-0.6(Li_(1/2)Nd_(1/2))TiO_3陶瓷烧结和介电性能的影响

研究了烧结助剂BaCu(B2O5)(BCB)对0.4CaTiO3-0.6(Li1/2Nd1/2)TiO3(CLNT)介质陶瓷的烧结特性、相组成、微观形貌及介电性能的影响。结果表明:添加少量的BCB能使CLNT陶瓷的烧结温度从1300℃降低至1050℃。随着BCB添加量的增加,介电常数下降,频率温度系数向负值偏移。添加4wt%BCB的CLNT陶瓷在1050℃烧结2h,获得了最佳的介电性能:εr=96.5,tanδ=0.017,τf=-13.6ppm/℃,满足高介多层片式微波元器件的设计要求。     

添加剂对0.95MgTiO3-0.05CaTiO3陶瓷性能的影响

采用同相反应法分别制备了V2O5,Co2O3和ZnO氧化物掺杂的0.95MgTiO3-0.05CaTiO3(95MCT)介质陶瓷.研究了V2O5,Co2O3和ZnO氧化物掺杂对95MCT陶瓷烧结特性和介电性能的影响.结果表明:V2O5.Co2O3和ZnO氧化物掺杂的95MCT陶瓷的主晶相为MgTiO3和CaTiO3两相结构,无中间相MgTi2O5出现.V2O5,Co2O3和ZnO氧化物掺杂可以有效地降低95MCT陶瓷的烧结温度,提高致密化程度,降低介电损耗,调节温度系数.ZnO掺杂的95MCT陶瓷性能最好:烧结温度降低至1 250℃,介电常数为21.7,烧结密度可达3.8g、cm3(理论密度的98.4%),介电损耗降低至10-5,温度系数为0.12×10-5/℃.     

(Ba_(1-α)Sr_α)_(4.8)(Sm_(0.7)La_(0.3))_(8.8)Ti_(18)O_(54)陶瓷的微波介电性能

采用固相合成法制备了(Ba(1-α)Srα)4.8(Sm0.7La0.3)8.8Ti18O54(α=0.1～0.5)系陶瓷,表征了该陶瓷的相组成和显微结构,测试了微波介电性能.结果表明:α=0.3时,(Ba(1-α)Srα)4.8(Sm0.7La0.3)8.8Ti18O54系陶瓷为单相的新钨青铜结构固溶体.α>0.3时,相继出现了第二相BaLa2Ti4O12和La0.66TiO2.993.随α的增加,(Ba(1-α)Srα)4.8(Sm0.7La0.3)8.8Ti18O54系陶瓷的相对介电常数(εr)先增大后有所波动,品质因数(Qf)先增大后减小,谐振频率温度系数(τf)单调减小.α=0.3时,在1 350℃烧结的陶瓷的微波介电性能最佳:εr=98.77,Qf=5184GHz,τf=10.9×10-6/℃,优于不掺杂的BaO-Sm2O3-TiO2陶瓷的.     

ZnO掺杂量与烧结温度对SnO2–Ta2O5–ZnO压敏变阻材料性能的影响

以SnO2、Ta2O5和ZnO粉为原料,通过传统陶瓷固相反应烧结法制备了压敏变阻材料,实验中ZnO含量为0～2.00%(摩尔分数),烧结温度控制在1 300～1500℃并保温2 h。研究了ZnO掺杂量和烧结温度对材料的组成、微观结构和电学性能的影响。结果表明:在温度一定条件下,随着ZnO掺杂量的增加,材料的非线性系数、压敏电压先增大后减小;在ZnO含量一定时,随着烧结温度从1 300℃升至1 450℃,材料的非线性系数、压敏电压先增大后减小。ZnO掺杂量为0.50%时,在1450℃烧结得到的样品的非线性系数最高(6.2),漏电流最小(262μA/cm2),压敏电压较高(83V/mm)。     

水基流延片式ZnO压敏电阻器低温共烧工艺及其性能

用环境扫描电子显微镜（ESEM）、X射线衍射（XRD）和X射线能谱（EDXS）等研究了水基流延片式ZnO压敏电阻器的低温共烧工艺及其对微观结构和电学性能的影响规律。ESEM分析结果表明：当等静压压力为60 MPa时,Ag电极与流延膜生坯界面结合紧密,Ag电极分布连续,900℃共烧时,未出现开裂、分层,两者收缩率接近。EDXS和XRD分析结果表明：900℃共烧时,Ag在片式压敏电阻器中以单质形式存在,流延膜与Ag电极化学兼容性良好,且在共烧界面处未发现有明显的Ag离子扩散。该流延膜可以与Ag电极在900℃时实现低温共烧,用此制备的片式ZnO压敏电阻器具有良好的压敏性能：压敏电压V1mA=6.1 V,非线性系数α=28.1,漏电流IL=0.15μA。     

Electrical characterization of ZnO multilayer varistors on the nanometre scale with conductive atomic force microscopy

The conductivity of ZnO–varistor ceramics has been analyzed with conductive atomic force microscopy (C-AFM) under atmospheric conditions by measuring the current at different voltages and positions in zinc oxide-based multilayer varistors (MLVs). It is possible to detect individual ZnO grains on the polished sample surface in the AFM topography mode as well as in the two-dimensional current images. Additionally local current–voltage (IV) curves revealed details of the electrical behaviour of the material. To correlate the laterally resolved current image with grain orientations, electron backscattering diffraction (EBSD) has been performed. Beside the well-known varistor behaviour specific influence of the local microstructure has been found.     

添加Nd2O3对氧化锌压敏阀片电性能与显微组织的影响

研究了微量Nd2O3添加剂对氧化锌压敏阀片的压敏电位梯度、漏电流和压比的影响,并对其显微组织进行了分析研究,从理论上探讨了Nd2O3对氧化锌压敏阀片电性能与组织的作用机理。研究结果表明:当Nd2O3的摩尔分数为0.04％时,氧化锌压敏阀片的压敏电位梯度最高,漏电流最小,压比最低,具有优良的综合电性能。其原因是Nd2O3加入到氧化锌压敏阀片中,使晶粒尺寸减小所致。     

Low-temperature sintering and electrical properties of BBSZ glass-doped ZnO-based multilayer varistors

The effect of Bi₂O₃-B₂O₃-SiO₂-ZnO glass (denoted as BBSZ) content on the densification, microstructure, and electrical properties of ZnO-based multilayer varistors (MLVs) has been investigated. In ZnO-based (MLVs), BBSZ acted as a promoter in ZnO grain growth, which increased the grain size of ZnO, resulting in a decrease in breakdown voltage. Results showed that the adding of BBSZ glass had an improvement in densification and overall properties of MLVs. It was found that a maximum value of 5.45 g/cm³ of the bulk density and the optimum properties (V_1mA = 27.28 V, α = 40.33, I_L = 0.75 μA, I_p = 35 A) of ZnO-based MLVs were achieved with 3 wt% BBSZ glass sintered at 925°C for 3 hours.     

Electrical Properties of Multilayer-Chip ZnO Varistors in a Moist-Air Environment

Multilayer-chip varistors were prepared using the ZnO-glass system by applying tape casting technology. The effect of processing conditions on the multilayer ceramic microstructure and electrical properties was studied. The location, size, and density of the pores within the multilayer structure were examined by scanning electron microscopy and the displacement method using distilled water. The experimental results showed that the electrical properties of a multiplayerchip varistor could be influenced substantially by the porosities associated with environmental moisture in the range ≅15%–95% relative humidity at 25°C. Such an effect can cause substantial current leakage as well as the separation of the I–V curves into four regions, i.e., pre-breakdown, linear, breakdown, and upturn. A proposed pore model and equivalent circuit for the multilayer-chip ZnO varistors. have been simulated with a commercial varistor and a serial resistance to demonstrate the observed I–V phenomena.     

Preparation and electrical properties of multilayer ZnO varistors with water-based tape casting

Multilayer ZnO varistors were prepared by water-based tape casting with water-soluble acrylic as binders. Zeta potentials of the doped ZnO suspensions as a function of pH with and without dispersant were measured. Viscosity measurements were used to find the optimum dispersant concentration needed to prepare a stable slurry. Viscosity properties of the tape casting slurry were investigated. The results showed that aqueous acrylic binders have shear thinning properties suitable for tape casting of ceramic powders. Scanning electron microscopy (SEM) studies revealed that the green sheets have a smooth defect-free surface and that the multilayer varistor (MLV) ceramics prepared by water-based tape casting have a fine grain microstructure with a uniform grain size and dopant distribution. The multilayer ZnO varistors prepared by water-based tape casting display comparable good electrical properties to those prepared by solvent-based tape casting. This is believed to be attributed to the well dispersed water-based slurry, which makes more uniform dopant distribution throughout the multilayer ZnO varistors. Therefore, water-based tape casting is suitable for the manufacture of high performance multilayer ZnO varistors.     

The effect of SiO2 on electrical properties of low‐temperature‐sintered ZnO–Bi2O3–TiO2–Co2O3–MnO2‐based ceramics

ZnO–Bi₂O₃–TiO₂–Co₂O₃–MnO₂‐based (ZBTCM) varistors were fabricated via the conventional solid‐state method, and the effect of SiO₂ content on the phase transformation, microstructure, and electrical properties of the ZBTCM had been investigated. Results showed that this varistor can be sintered at a low temperature of 880°C with a high sintering density above 0.95 of the ZnO theoretical density. In these components, SiO₂ acts as a controller in ZnO grain growth, decreasing the grain size of ZnO from 3.67 to 1.92 μm, which in turn results in an increase in breakdown voltage E_1mA from 358.11 to 1080 V/mm. On the other hand, SiO₂ has a significant influence on the defect structure and component distribution at grain‐boundary regions. When SiO₂ content increases from 0 to 4 wt%, the value of the interface state density (N_s) increases sharply. At the same time, the electrical properties are improved gradually, and reach an optimized value with the nonlinear coefficient (α) up to 54.18, the barrier height (?_b) up to 2.90 eV, and the leakage current (I_L) down to 0.193 μA/cm².     

室温固相合成掺杂ZnO纳米粉体制备ZnO压敏电阻

以金属离子盐和草酸为原料,采用室温固相化学反应合成掺杂ZnO前驱物,根据DSC-TG分析结果,将其在450℃热分解2 h,得到掺杂ZnO粉体,并用此粉体制备了片式ZnO压敏电阻。借助XRD、TEM、BET等检测手段对粉体产物的物相、形貌、粒度等进行了表征。研究了烧结温度对ZnO压敏电阻电性能的影响。结果表明,所制备的粉体为平均粒径24 nm左右、颗粒呈球状、分散性好的纤锌矿结构掺杂ZnO。在1 080℃烧结时,ZnO压敏电阻的综合电性能达到最佳,电位梯度为791.64 V/mm,非线性系数为24.36,漏电流为43μA。     

Al-doped ZnO varistors prepared by a two-step doping process

ABSTRACT

It is difficult to dope Al into main grains of ZnO varistor ceramics, especially for small doping amount. Generally, all raw materials including Al dopant are directly mixed together and sintered into ceramics. However, in this direct doping process, Al is apt to stay in grain boundaries, and almost does not enter grains. This does harm to the electrical properties of ZnO varistors. In this paper, we proposed a two-step doping process. Al₂O₃ powder was first mixed only with a part of the ZnO powder and pre-sintered. The pre-sintered powder was mixed with other additives such as Bi₂O₃ and the rest ZnO. Then ZnO varistor ceramics were prepared via solid state sintering processes. Results showed that two-step doped ZnO varistors exhibited improved electrical properties with a significant increased nonlinear coefficient and a great decreased leakage current compared to directly doped ones because more Al was incorporated into ZnO grains.