Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

Flip chip solder joint reliability analysis using viscoplastic and elastic-plastic-creep constitutive models

Both elastic-plastic-creep and viscoplastic constitutive models may be used for inelastic deformation analysis of solder joints. In this paper, a phenomenological approach using elastic-plastic-creep analysis and an Anand viscoplastic model is reported for solder joint reliability. Flip chip soldered assemblies with 63Sn-37Pb solder joints were subjected to a thermal cyclic loading condition of -40 to +125/spl deg/C to assess the solder joint fatigue performance. In the finite-element modeling, the viscoplastic strain energy density per cycle obtained from the viscoplastic analysis is compared with the inelastic (plastic and creep) strain energy density per cycle calculated from the elastic-plastic-creep analysis. The inelastic (plastic+creep and viscoplastic) strain energy density extracted from the finite-element analysis results, at the critical solder joint location, were used as a failure parameter for solder fatigue models employed. It was found that the predicted solder joint fatigue life has a better correlation to the first failure or first-time-to-failure result.     

印制板上形成凸块的倒芯片安装技术

该文概述了在印制板(PWB)上形成倒芯片安装用的凸块的方法和工艺条件,并进行可靠性试验和评价,确认了Boss B~2it 技术可以实现低成本倒芯片安装。     

基于ANSYS的挠性基板叠装互联组件热分析

长期使用环境中交变温度载荷引起的结构热疲劳会显著影响挠性基板叠装互联组件的结构强度和使用寿命.以挠性基板叠装互联组件为研究对象,基于ANSYS软件参数化建模方法建立了挠性基板叠装互联组件三维有限元模型,针对互联组件六种内部芯片布局方案进行了互联结构热特性分析并进行对比.然后基于正交试验方法分析了多种影响因素对互联组件热...     

Flip chip on board solder joint reliability analysis using 2-D and3-D FEA models

This study investigates the effects of employing different two-dimensional (2-D) and three-dimensional (3-D) finite element analysis (FEA) models for analyzing the solder joint reliability performance of a flip chip on board assembly. The FEA models investigated were the 2-D-plane strain, 2-D-plane stress, 3-D-1/8th symmetry and 3-D-strip models. The different stress and strain responses generated by the four different FEA models were applied to various solder joint low cycle fatigue life prediction relationships. The investigation shows that the 2-D-plane strain and 2-D-plane stress models gave the highest and lowest solder joint strains, respectively. The 3-D-strip and 3-D-1/8th symmetry model results fall in between the 2-D-plane strain and 2-D-plane stress model results. The 3-D-1/8th symmetry model agrees better with the 2-D-plane strain model, while the 3-D-strip model agrees better with the 2-D-plane stress model results. The results for the fatigue life prediction analyses also show similar trends     

UV nanoimprint using flexible polymer template and substrate

Nano to micro-sized patterns were formed on a flexible polymer substrate using a flexible UV imprint stamp. A 6 in. diameter flexible UV nanoimprint template was fabricated using PVC hot embossing and DLC coating. Using the UV nanoimprint process with the DLC coated PVC template, nano to micro-sized patterns were clearly formed on the flexible PET substrate without a residual layer, due to the antistiction properties and high mechanical hardness of the DLC coating. By depositing a Cr layer on the imprinted resist pattern and lifting it off, Cr metal patterns were fabricated on the PET substrate.     

Effects of Heating Rate on Material Properties of Anisotropic Conductive Film (ACF) and Thermal Cycling Reliability of ACF Flip Chip Assembly

In this paper, the effects of heating rate during anisotropic conductive film (ACF) curing processes on ACF material properties such as thermomechanical and rheological properties were investigated. It was found that as the heating rate increased, the coefficient of thermal expansion (CTE) of the ACF increased, and the storage modulus and glass transition temperature $(T _{g})$ of the ACF decreased. Variation of the ACF material properties are attributed to cross-linking density, which is thought to be related with the ACF density. In addition, as the heating rate increased, the minimum viscosity of the ACF decreased and the curing onset temperature increased during the curing process. The similar phenomenon was also found in in-situ contact resistance measurement. As the heating rate increased, contact resistance establishing temperature increased and the contact resistances of the ACF flip chip assemblies decreased. The decrease in contact resistance was due to larger conductive particle deformation which leads to larger electrical contact area. The effect of the heating rate of ACFs on thermal cycling (T/C) reliability of flip chip assemblies was also investigated. As the heating rate increased, the contact resistances of the ACF flip chip assembly rapidly increased during the T/C test. The T/C reliability test result was analyzed by two terms of shear strain and conductive particle deformation. Reduced gap of joints due to reduced ACF viscosity resulted in larger shear strain. Moreover, many cracks were observed at metal-coated layers of conductive particles due to larger deformation.      

Flip chip on board: assessment of reliability in cellular phone application

Flip chips are generally seen as a potential future "packaging" option providing an alternative to chip scale packages. In this work, the reliability of flip chip assemblies was analyzed using daisy chain test components on a schematic test vehicle designed to emulate a cellular phone environment printed wiring board (PWB). The flip chip components were assembled in a standard surface mount technology process, where the flip chip bumps were first dipped in a flux film. A test matrix consisting of a number of flip chip test components with different input/output configurations, PWBs, fluxes, and underfills was built up. The assemblies were tested for potential damage to the flip chips and their interconnects by thermal cycling and by mechanical shock in a drop. After testing, the root causes of the failures were analyzed. As a separate task, the stress/strain generation that occurs in the flip chips in the drop test was analyzed using simulation, in order to find the critical locations on the test PWB.     

High-gain W-band-printed antenna on flexible substrate

This article demonstrates a novel type of series-fed planar antenna array for a W-band (70 GHz) application. The proposed architecture is a 5-element antenna array with 10 numbers of gap-coupled parasitic patches in microstrip configuration over a thin, flexible and bio-compatible substrate named LCP (liquid crystal polymer). A detailed design methodology with all fabrication constraints has been elaborated on here. Full wave analysis of the whole structure has been carried out in the FEM-based 3D electromagnetic (EM) solver ANSYS HFSS Suite V.19.2. Parametric simulations were studied to achieve the optimized values of all design parameters. Further, an empirical electrical equivalent circuit model is proposed for the antenna array, and it was validated with the simulation results obtained from the FEM solver. Two prototypes have been fabricated, and measurements were carried out to fetch all the designed antenna parameters. The proto version of the antenna offers peak directive gain of about 19 dBi with better than 22 dB of return loss and 80% radiation efficiency for the frequency range of 67–85 GHz. Experimental and simulated results closely match each other. Small deviations are attributed to practical imperfections incurred by fabrication tolerances, measurement inaccuracies, testing, assembly-related issues and so forth. Finally, the current research work is compared with the recently reported literature.     

Effect of misalignment on electrical characteristics of ACF joints for flip chip on flex applications

The effect of misalignment on the electrical properties of anisotropic conductive film (ACF) joints is investigated in this work. It is found that along with the increase of misalignment, the connection resistance of ACF joints increases. When the misalignment in x-direction is less than 5 μm, the increase rate of connection resistance is quite large. Then, along with the severity of misalignment, the increase rate becomes smaller. Finally, when the misalignment is close to 20 μm, the increase rate rises again. The Holm's electric contact theory is used for understanding the connection resistance variation. On the other hand, with the increase of misalignment in x-direction, the insulation resistance between ACF joints decreases. If the misalignment exceeded 10 μm, the decrease is prominent for the Ni particle ACF joints. This phenomenon can be explained by the effect of dielectric damage of the epoxy.Computer programs are also developed to calculate the variation of the probability of open and shorting after misalignment and predicate the maximum misalignment tolerance. The results show that the open and shorting probability increase abruptly after misalignment. On the view of pad parameters, the open probability is mainly related to the pad area, while the pads gap is critical to the shorting probability. Large pads gap (small pad width) can reduce the shorting probability obviously. On the other hand, enlarging the pad area by increasing pad length decreases the open probability significantly. So comparing to square shape pad, rectangle shape pad can reduce the failure probability greatly.     

Enhanced printed temperature sensors on flexible substrate

In this paper we present the development of enhanced printed temperature sensors on large area flexible substrates. The process flow is a fully screen printed technology that uses exclusively solution-processed materials. These Screen printed temperature sensors are based on resistive pastes integrated in a Wheatstone bridge circuit. Substrate is a commercial Poly Ethylene Naphtalate (PEN) with a thickness of 125 µm. Functional temperature sensors are demonstrated and characterized with good electrical properties, showing a good sensitivity of 0.06 V/°C at V_in=4.8 V. This sensitivity is enhanced by the annealing and the O₂ plasma treatment. Based on this temperature sensor, we have developed a demonstrator for human body temperature detection.     

薄膜基板芯片共晶焊技术研究

共晶焊是微电子组装技术中的一种重要焊接工艺,在混合集成电路中得到了越来越多的应用。文中简要介绍了共晶焊接的原理,分析了影响薄膜基板与芯片共晶焊的各种因素,并且选用Ti/Ni/Au膜系和AuSn焊料,利用工装夹具在真空环境下通入氮、氢保护气体的方法进行薄膜基板芯片共晶焊技术的研究。     

High-density CMOS interconnect realized on flexible organic substrate

High-density interconnect integrated circuits (ICs) have been realized on flexible organic substrate with the demonstration of excellent electrical yield and well maintained reliability. Long metal-via chain structures were pre-fabricated with 0.18-/spl mu/m Cu-backend technology on Si-substrate and later transferred onto the organic substrates with wafer-transfer technology. By optimizing the transfer process with thin FR-4 (4 mil /spl ap/0.1 mm), our results demonstrate that both Cu/USG and Cu/low-/spl kappa/ [Black-Diamond (BD)]-based interconnects can be reliably realized over the organic substrate. For via chain structures with via size /spl sim/0.26 /spl mu/m and via number /spl sim/10/sup 4/, the yields were /spl ges/90% and 85% at room temperature and at 100/spl deg/C, respectively. The dielectric breakdown field of the Cu/USG transferred interconnect ICs has been characterized to be /spl ges/5 MV/cm, which is comparable with the results on Si-substrate.     

柔性基底印刷叉指电容的阻抗特性研究

为降低电容制作成本,采用丝网印刷的方式在柔性PET基底上印制出可用于较高频段范围的叉指电容。首先利用电磁仿真软件设计出叉指电容的结构;然后通过实验研究了工艺参数对印刷薄膜电阻值的影响和油墨种类对印刷叉指电容阻抗特性的影响,确定合适的丝网印刷工艺参数和导电性能良好的油墨;最后,采用上述油墨和工艺参数印制了不同结构参数的叉指电容,测试了其阻抗特性,分析了不同结构参数对其阻抗特性的影响。实验结果表明:印刷叉指电容的阻抗特性与理论仿真结果一致;叉指电容所有结构参数中,指的长度和指的个数对其阻抗特性影响较大,印制的叉指电容在100~600 MHz范围内具有较好的阻抗特性。     

Low temperature Solution-Processed ZnO film on flexible substrate

Transparent conductive ZnO films were directly deposited on unseeded polyethersulfone (PES) substrates with a spin-spray method using aqueous solution at a low substrate temperature of 85 °C. All ZnO films were crystalline with wurtzite hexagonal structure and impurity phases were not detected. ZnO films deposited without citrate ions in the reaction solution had a rod array structure. In contrast, ZnO films deposited with citrate ions in the reaction solution had a continuous, dense structure. The transmittance of the ZnO films was improved from 11.9% to 85.3% as their structure changed from rod-like to continuous. After UV irradiation, the ZnO films with a continuous, dense structure had a low resistivity of 9.1×10⁻³ Ω cm, high carrier concentration of 2.7×10²⁰ cm⁻³ and mobility of 2.5 cm² V⁻¹ s⁻¹.     

Fabrication and characterization of bilayer metal wire-grid polarizer using nanoimprint lithography on flexible plastic substrate

In this work, we demonstrate the fabrication of bilayer metal wire-grid polarizers and the characterization of their performance. The polarizers with 200 nm period were fabricated on flexible plastic substrates by nanoimprint lithography (NIL), followed by aluminum deposition. Transmission efficiency over 0.51 and extinction ratio higher than 950 can be achieved in the visible range when the aluminum thickness of the polarizer is 100 nm. The fabrication process only involves direct imprinting on flexible plastic substrates and aluminum deposition, without any resist spin-coating, lift-off, and etching processes, which is much simpler, less costly, and applicable to large volume production.     

Bendability of single-crystal Si MOSFETs investigated on flexible substrate

This letter reports on a device layer transfer (based on thermal bonding and grinding backside Si) process and device characteristics of Si MOSFETs on a flexible substrate, focusing mainly on the mechanical bendability of the device and resistance to fatigue. The results demonstrated a well-optimized bonding process, as indicated by the nearly indiscernible performance difference (e.g., subthreshold slope, V/sub th/, and I/sub dsat/) before and after the bonding of Si with the flexible substrate. The device characteristics indicate excellent bendability of Si MOSFETs on flexible substrate (e.g., for radius tested down to /spl plusmn/72 mm) and good immunity to fatigue (e.g., negligible performance drift tested up to /spl sim/10/sup 3/ bending cycles with a radius of /spl plusmn/126 mm). Results suggest the feasibility of this approach in achieving high-performance MOSFETs for applications in performance-sensitive and flexible electronics.     

基于纳米压印PET基底的高效柔性有机电致发光器件

为了克服现有的以玻璃为基底、ITO为电极的有机电致发光器件（OLED）的韧性差、对裂纹缺陷敏感等固有缺点,对现有的OLED器件结构进行优化。本文提出了以PET为基底,旋涂高导PEDOT：PSS作为阳极的高效柔性OLED器件结构。并在此基础上,通过纳米压印蛾眼模板将光耦合结构引入器件,提高器件的光取出效率。此绿光FOLED器件在亮度为1 000 cd·m^-2时,功率效率为36.10 lm·W^-1。在此基础上,通过纳米压印引入光耦合结构的柔性OLED器件表现出良好的光电性质,在亮度为1 000 cd·m^-2时,功率效率可达到80.46 lm·W^-1。并且这种绿光柔性OLED器件在以器件半边长为曲率半径180°弯折200次后亮度衰减很少。此种高导PEDOT：PSS电极和柔性PET基底可以成为较好的ITO透明电极和刚性玻璃基底的替代物,为生产可穿戴式设备提供了可能。     

Damage predictions in a chip resistor solder joint on flexible circuit board

Flexible circuit boards are being widely used in the electronic packages. Solders are often used to assemble chip resistors and other components on them. In practice, solder alloys work in high homologous temperatures and experience cyclic temperature loadings. As a result, damage may accumulate in solder materials quickly and this will eventually lead to the failure of the solder joints. In this work, computer modelling technique has been used to predict such damage accumulations in chip resistor solder joints under a range of thermal cycling conditions. It has been documented that the higher and the lower dwell temperatures of a thermal cycle dominate the damages in solder joints. Both the ramp time and the cycle duration have strong influence on the damage accumulation. In general, faster ramp time and longer cycle duration cause more damages. The types of materials used to produce flexible circuit board have also significant impact on the damage accumulation. Polyimide (PI), Polyethylene Naphthalate (PEN) and Liquid Crystal Polymer (LCP) based flexible circuit boards have been compared for their effect on damage in solder joints and the results show that the highest damage could be found in the chip resistor solder joint on the PI-based flexible circuit boards and least damage could be found for the LCP based flexible circuit boards. The results also show that the thicknesses of the constituent layers of different materials in flexible circuit boards are linearly proportional to the damage accumulation in solder joints.