Highly Manufacturable and Reliable HfSiON N-FET With Poly-Si/a-Si Stacked Gate for LSTP Applications

We have proposed a novel poly-Si/a-Si/HfSiON transistor to enhance reliabilities without performance degradation for a 65-nm-node low standby power (LSTP) application. By insertion of a thin amorphous-Si layer between the Poly-Si gate electrode and HfSiON, both phosphorus penetration from gate electrode and a reaction at gate electrode/HfSiON interface are successfully suppressed, so that positive bias temperature instability, one of the biggest issues for high-k gate dielectric, is drastically improved by two orders of magnitude. By carefully optimizing the gate stack structure of HfSiON, the HfSiON device can satisfy both lower gate leakage and gate-induced drain leakage at the same time. As a result, an excellent I_on- I_standby (= I_g + l_off) characteristic can be achieved, compared to the conventional SiON device. The a-Si insertion technique can realize the combination between the high-k gate dielectric and Poly-Si for future LSTP applications.     

Layered (C6H5CH2NH3)2CuBr4 Perovskite for Multilevel Storage Resistive Switching Memory

Although there have been attempts to use non‐lead based halide perovskite materials as insulating layers for resistive switching memory, the ratio of low resistance state (LRS) to high resistance state (HRS) ( = ON/OFF ratio) and/or endurance is reported to be mostly lower than 10³. Resistive switching memory characteristics of layered (BzA)₂CuBr₄ (BzA = C₆H₅CH₂NH₃) perovskite with high ON/OFF ratio and long endurance are reported here. The X‐ray diffraction (XRD) pattern of the deposited (BzA)₂CuBr₄ layer shows highly oriented (00l) planes perpendicular to a Pt substrate. An Ag/PMMA/(BzA)₂CuBr₄/Pt device shows bipolar switching behavior. A forming step at around +0.5 V is observed before the repeated bipolar switching at the SET voltage of +0.2 V and RESET voltage of ‐0.3 V. The ON/OFF ratio as high as =10⁸ is monitored along with an endurance of ≈2000 cycles and retention time over 1000 s. The high ON/OFF ratio enables multilevel storage characteristics as confirmed by changing the compliance currents. Ohmic conduction at the LRS and Schottky emission at HRS are involved in electrochemical metallization process. The bipolar resistive switching property is retained after storing the device at ambient condition under relative humidity of about 50% for 2 weeks, which indicates that (BzA)₂CuBr₄ is stable memory material.     

High Injection Efficiency and Low-Voltage Programming in a Dopant-Segregated Schottky Barrier (DSSB) FinFET SONOS for nor-type Flash Memory

A dopant-segregated Schottky barrier (DSSB) FinFET silicon–oxide–nitride–oxide–silicon (SONOS) for nor-type Flash memory is successfully demonstrated. Compared with a conventional FinFET SONOS device, the DSSB FinFET SONOS device exhibits high-speed programming at low voltage. The sharp dopant-segregated Schottky contact at the source side can generate hot electrons, and it can be used to provide high injection efficiency at low voltage without any constraint on the choice of the proper gate and drain voltage. The DSSB FinFET SONOS device is therefore a promising candidate for nor-type Flash memory with high-speed and low-power programming.      

A bootstrapped bipolar CMOS (B2CMOS) Gate forlow-voltage applications

This paper reports on a BiCMOS logic gate which combines bootstrapping and transient saturation techniques to achieve full swing operation down to 1.1 V supply voltage. The proposed B²CMOS uses a conventional (noncomplementary) BiCMOS process. HSPICE simulations have been used to compare the B²CMOS to CMOS, BiNMOS, and BS-BiCMOS for sub-0.5 μm BiCiMOS technologies. Simulation results have shown that the B²CMOS gate outperforms CMOS, BiNMOS, and BS-BiCMOS gates at 3 V and below. The crossover capacitance/fanout of the B²CMOS gate is 100 fF (i.e., fanout of 4) at 1.5 V. The delay-to-load sensitivity of the B²CMOS is 220 ps/pF (8 ps/fanout) which is one order of magnitude smaller than that of CMOS at 1.5 V     

超薄Si3N4/SiO2（N/O）stack栅介质及器件

成功制备了EOT(equivalent oxide thickness)为2.1nm的Si3N4/SiO2(N/O) stack栅介质,并对其性质进行了研究．结果表明，同样EOT的Si3N4/SiO2 stack栅介质和纯SiO2栅介质比较，前者在栅隧穿漏电流、抗SILC性能、栅介质寿命等方面都远优于后者．在此基础上,采用Si3N4/SiO2 stack栅介质制备出性能优良的栅长为0.12μｍ的CMOS器件，器件很好地抑制了短沟道效应．在Vds=Vgs=±1.5V下，nMOSFET和pMOSFET对应的饱和电流Ion分别为584.3μA/μｍ和－281.3μA/μｍ，对应Ioff分别是8.3nA/μｍ和－1.3nA/μｍ．     

超薄Si3N4/SiO2(N/O) stack栅介质及器件

成功制备了EOT(equivalent oxide thickness)为2.1nm的Si3N4/SiO2(N/O) stack栅介质,并对其性质进行了研究.结果表明,同样EOT的Si3N4/SiO2 stack栅介质和纯SiO2栅介质比较,前者在栅隧穿漏电流、抗SILC性能、栅介质寿命等方面都远优于后者.在此基础上,采用Si3N4/SiO2 stack栅介质制备出性能优良的栅长为0.12μm的CMOS器件,器件很好地抑制了短沟道效应.在Vds=Vgs=±1.5V下,nMOSFET和pMOSFET对应的饱和电流Ion分别为584.3μA/μm和-281.3μA/μm,对应Ioff分别是8.3nA/μm和-1.3nA/μm.     

Fluorine Passivation in Gate Stacks of Poly-Si/TaN/HfO2 (and HfSiON/HfO2)/Si Through Gate Ion Implantation

Fluorine passivation in poly-Si/TaN/HfO₂/p-Si and poly-Si/TaN/HfSiON/HfO₂/p-Si gate stacks with varying TaN thickness through gate ion implantation has been studied. It has been found that when TaN thickness was less than 15 nm, mobility and subthreshold swing improved significantly in HfO₂ nMOSFETs; while there was little performance improvement in HfSiON/HfO₂ nMOSFETs due to the blocking of F atoms by the HfSiON layer in gate dielectrics, as has been proved by the electron energy loss spectroscopy mapping     

Energy Efficient and Reliable ARQ Scheme (E^2R-ACK) for Mission Critical M2M/IoT Services

Wireless sensor networks (WSNs) are the main infrastructure for machine to machine (M2M) and Internet of thing (IoT). Since various sophisticated M2M/IoT services have their own quality-of-service (QoS) requirements, reliable data transmission in WSNs is becoming more important. However, WSNs have strict constraints on resources due to the crowded wireless frequency, which results in high collision probability. Therefore a more efficient data delivering scheme that minimizes both the transmission delay and energy consumption is required. This paper proposes energy efficient and reliable data transmission ARQ scheme, called energy efficient and reliable ACK (E \(^2\) R-ACK), to minimize transmission delay and energy consumption at the same time. The proposed scheme has three aspects of advantages compared to the legacy ARQ schemes such as ACK, NACK and implicit-ACK (I-ACK). It consumes smaller energy than ACK, has smaller transmission delay than NACK, and prevents the duplicated retransmission problem of I-ACK. In addition, resource considered reliability (RCR) is suggested to quantify the improvement of the proposed scheme, and mathematical analysis of the transmission delay and energy consumption are also presented. The simulation results show that the E \(^2\) R-ACK scheme achieves high RCR by significantly reducing transmission delay and energy consumption.     

P-Type Floating Gate for Retention and P/E Window Improvement of Flash Memory Devices

A flash memory with a lightly doped p-type floating gate is proposed, which improves charge retention and programming/erase (P/E) V_th window. Improvement in P/E window is enhanced for cells with smaller capacitance coupling ratio, which is important for future scaled flash memory cells. Both device simulation and experimental verification are presented.     

WSi_2栅和Si栅CMOS／BESOI的高温特性分析

用厚膜ＢＥＳＯＩ（ＢｏｎｄｉｎｇａｎｄＥｔｃｈ－ｂａｃｋＳｉｌｉｃｏｎ－Ｏｎ－Ｉｎｓｕｌａｔｏｒ）制备了ＷＳｉ２栅和Ｓｉ栅４００７ＣＭＯＳ电路，在室温～２００℃的不同温度下测量了其Ｐ沟、Ｎ沟ＭＯＳＦＥＴ的亚阈特性曲线，分析了阈值电压和泄漏电流随温度的变化关系。     

Comparative Analysis of Double Gate Junction Less (DG JL) and Gate Stacked Double Gate Junction Less (GS DG JL) MOSFETs

Semiconductors - The quest for downscaling of devices has led to novel configurations with better performance parameters of which Junction Less (JL) MOSFET is an important configuration regarding...     

Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model

The reverse read method and second-bit effect of the 2-bit/cell nitride-trapping device are comprehensively studied by a quasi-two-dimensional (2-D) model. Based on this model, analytical equations are derived to simulate the surface potential of the device with locally injected electrons. This model indicates that the reverse read method exploits the local drain-induced barrier lowering (DIBL) effect that reduces the potential barrier produced by the locally injected electrons. The experimental results of the two-region behavior of second-bit effect can be well explained and simulated by this analytical model. Two-dimensional numerical calculations are also carried out to verify these analytical equations. The impact of short-channel effect on the second-bit effect is also examined.     

Carbon-Doped Polysilicon Floating Gate for Improved Data Retention and P/E Window of Flash Memory

We propose a novel approach to engineering floating gates (FGs) of Flash memory cells, namely, carbon incorporation into polysilicon FGs. This technique demonstrated an improvement in retention and a larger program/erase $V_{t}$ window, particularly for smaller capacitance coupling ratio cells, which is important for future scaled Flash memory cells.      

Channel width dependence of hot electron injection program/hot hole erase cycling behavior in silicon-oxide-nitride-oxide-silicon (SONOS) memories

The channel width dependence of hot electron injection program/hot hole erase cycling behavior in silicon-oxide-nitride-oxide-silicon (SONOS) memories is investigated. While the trapped charge profile-dependent overerasure is observed in 10-μm-wide device, it is suppressed in 0.22-μm-wide device. Both the overerasure suppression and gradual positive threshold voltage shift in narrow device are explained as an elevated hot hole injection efficiency followed by more pronounced redistribution of the hole profile in the channel-center and the suppression of the lateral migration of injected holes in the channel-edge, by combining the measured endurance characteristics and TCAD simulation results. Main physical mechanisms are three-dimensional distribution of the electric field by gate/drain voltage, increasing interface states, and their trapped charge with cycling in the channel-edge.     

TiO_2/SiO_2和TiO_2/SiO_xN_y层叠结构高k栅介质比较研究

以射频磁控溅射为主要工艺,制备了TiO2/SiO2和TiO2/SiOxNy两种层叠结构栅介质。对C-V特性和漏电特性的测试表明,SiO2和SiOxNy等界面层的引入有效地降低了TiO2栅介质电荷密度及漏电流,而不同层叠结构的影响主要通过界面电学性能的差异体现出来。对漏电特性的进一步分析显示,TiO2/SiO2结构中的缺陷体分布和TiO2/SiOxNy结构中的缺陷界面分布是导致电学性能差异的主要原因。综合比较来看,TiO2/SiOxNy结构栅介质在提高MOS栅介质性能方面有更大的优势及更好的前景,有助于拓展TiO2薄膜在高k栅介质领域的应用。     

A Comparative Study of HfTaON/SiO2 and HfON/SiO2 Gate Stacks With TaN Metal Gate for Advanced CMOS Applications

The electrical characteristics of a novel HfTaON/SiO₂ gate stack, which consists of a HfTaON film with a dielectric constant of 23 and a 10-Aring SiO₂ interfacial layer, have been investigated for advanced CMOS applications. The HfTaON/SiO₂ gate stack provided much lower gate leakage current against SiO₂ , good interface properties, excellent transistor characteristics, and superior carrier mobility. Compared to HfON/SiO₂, improved thermal stability was also observed in the HfTaON/SiO₂ gate stack. Moreover, charge-trapping-induced threshold voltage V _th instability was examined for the HfTaON/SiO₂ and HfON/SiO₂ gate stacks. The HfTaON/SiO₂ gate stack exhibited significant suppression of the V_th instability compared to the HfON/SiO₂, in particular, for nMOSFETs. The excellent performances observed in the HfTaON/SiO₂ gate stack indicate that it has the potential to replace conventional SiO₂ or SiON as gate dielectric for advanced CMOS applications     

Dual depletion CMOS (D/SUP 2/CMOS) static memory cell

A new type of static memory cell-dual depletion CMOS (D/SUP 2/MOS)-has been designed and fabricated using SOS wafers by the conventional CMOS/SOS technology. In contrast to the conventional CMOS static memory cell, which comprises six transistors, the new cell consists merely of four transistors and one data-line so that the cell area can be significantly reduced.     

基于等离子体氮化工艺的超薄栅氧化膜的电学特性和可靠性

介绍了利用MMT等离子体氮化工艺和炉管NO退火氮化工艺制备的超薄栅介质膜的电学特性和可靠性. 结合两种氮化工艺在栅介质膜中形成了双峰和单峰的氮分布. 通过漏极电流、沟道载流子和TDDB的测试,发现栅介质膜中双峰的氮分布可以有效提高器件的电学特性,更为重要的是可以极大提高器件的击穿特性. 这指明了延长掺氮氧化膜在超大规模集成电路器件栅介质层中应用的寿命,使之有可能进一步跟上技术的发展.     

TiSi_2薄膜的形成特性及TiSi_2/多晶硅复合栅结构的研究

本文用反应生成和合金靶溅射两种方法生成了TiSi_2薄膜,并对其形成特性进行了研究,同时将所形成的TiSi_(?)薄膜应用于MOSFET和MOS电容的制作中.结合电学性反的测量和TEM(横截面)在位观察,研究了TiSi_2/多晶硅复合栅结构的特性,发现当多晶硅厚度小于某一临界值时,经高温炉退火后,SiO_2/Si界面将会产生许多新的界面在,SiO_(?)层中会产生缺陷.对离于注入和热扩散掺杂的两种样品,多晶硅层厚度的这个临界值几乎是相同的.根据我们的实验和分析结果,证实了在TiSi_2薄膜的形成过程中所引入的应力是产生上述现象的基本原因.