体硅LDMOS漂移区杂质分段线性注入模型研究

提出了体硅LDMOS漂移区杂质浓度分布的一种二维理论模型,根据该模型,如果要使带有场极板的LDMOS得到最佳的性能,那么LDMOS漂移区的杂质浓度必须呈分段线性分布.用半导体专业软件Tsuprem-4和Medici模拟证明了该模型十分有效,根据该模型优化得到的新型LDMOS的击穿电压和导通电阻分别比常规LDMOS增加58.8%和降低87.4%.     

具有倾斜表面漂移区的SOI LDMOS的工艺设计

对一种具有倾斜表面漂移区SOI LDMOS的制造方法进行了研究,提出采用多窗口LOCOS法形成倾斜表面漂移区的新技术;建立了倾斜表面轮廓函数的数学模型,并开发了用于优化窗口尺寸和位置的计算机程序。TCAD 2-D工艺仿真验证了该技术的可行性。设计了漂移区长度约为15μm的SOI LDMOS。数值仿真结果表明,与RESURF结构器件相比较,其漂移区电场近似为理想的常数分布,并且击穿电压提高约8%,漂移区浓度提高约127%。由此可见,VLT是一种理想的横向耐压技术。     

阶梯掺杂薄漂移区RESURF LDMOS耐压模型

提出硅基阶梯掺杂薄漂移区RESURF LDMOS耐压解析模型.通过分区求解二维Poisson方程,获得阶梯掺杂薄漂移区的二维表面电场和击穿电压的解析表达式.借助此模型研究击穿电压与器件结构参数的关系,其解析与数值结果吻合较好.结果表明:在导通电阻相近情况下,阶梯掺杂漂移区LDMOS较均匀漂移区的击穿电压提高约20%,改善了击穿电压和导通电阻的折衷关系.     

A new analytical model for optimizing SOI LDMOS with step doped drift region

In this paper, a new theoretical breakdown model of SOI RESURF LDMOS with step drift doping profile is proposed. According to this model, the 2-D electric field distributions of drift regions are investigated for both the incompletely and completely depleted cases. The doping profile and step number are optimized to improve the breakdown voltage and reduce fabrication cost. Finally, SOI LDMOS with various step numbers have been made using a 3 μm-thick top silicon layer and a 1.5 μm-thick buried oxide layer. The experiment results indicate that two-step drift doping can enable increase in the breakdown voltage by as much as 40% and decrease in the on-resistance by as much as 16% in comparison to the conventional LDMOS with uniformly doped drift region.     

SOI基双级RESURF二维解析模型

提出了SOI基双级RESURF二维解析模型．基于二维Poisson方程，获得了表面电势和电场分布解析表达式，给出了SOI的双级和单级RESURF条件统一判据，得到RESURF浓度优化区(DOR，doping optimal region）,研究表明该判据和DOR还可用于其他单层或双层漂移区结构．根据此模型，对双级RESURF结构的降场机理和击穿特性进行了研究，并利用二维器件仿真器MEDICI进行了数值仿真．以此为指导成功研制了耐压为560V和720V的双级RESURF高压SOI LDMOS．解析解、数值解和实验结果吻合得较好．     

A novel double RESURF LDMOS for HVIC's

The viability of a fully implanted double RESURF technology using a linearly varying doping of p-layer at the surface [Electron. Lett. 32 (12) (1996) 1092-1093] is demonstrated for the first time. Incorporating such a layer allows the drift region charge to be doubled without degradation of breakdown voltage. Experimental results of a high-voltage LDMOS in such a technology show a reduction in the on-resistance by one-half of that of a conventional RESURF based structure.     

薄外延阶梯掺杂漂移区RESURF耐压模型

提出薄外延阶梯掺杂漂移区RESURF结构的耐压解析模型。借助求解二维Po isson方程,获得薄外延阶梯掺杂漂移区的二维表面电场和击穿电压的解析表达式。基于此耐压模型研究了不同阶梯漂移区数(n=1、2、3、5)的击穿特性,计算了击穿电压与结构参数的关系,其解析结果与数值结果吻合较好。在相同长度下,阶梯掺杂漂移区结构(n=3)击穿电压由均匀漂移区(n=1)的200 V提高到250 V,增加25%。该模型可用于薄外延阶梯掺杂和线性掺杂漂移区RESURF器件的设计优化。     

A new high voltage SOI LDMOS with triple RESURF structure

A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_sp is reduced from 16.5 to 13.8 mΩ·cm² in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV²/R_on.It reduces R_sp by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.     

具有n+浮空层的体电场降低LDMOS结构耐压分析

针对薄外延横向功率集成技术的发展,提出一种降低体内电场REBULF(REduced BULk Field)的新耐压技术,并设计了一例具有n 浮空层的REBULF LDMOS新结构.新耐压机理是通过嵌入在高阻衬底中的n 浮空层的等电位调制作用,提高源端体内低电场而降低漏端体内高电场使纵向电场重新分配,同时使衬底耐压提高.借助二维数值分析,验证了满足REBULF的条件为n 层的位置与衬底浓度的乘积不大于1×1012cm-2;在保证低的比导通电阻条件下,新结构较传统LDMOS结构击穿电压可提高75%以上.     

具有降场电极U形漂移区SOI-LDMOS的耐压特性

提出了一种具有降场电极 U形漂移区 SOI- L DMOS,借助 2 D泊松方程对其场分布进行解析分析和数值分析 ,结果证明该结构在与 RESURF结构相同的耐压下 ,具有器件长度小 ,漂移区浓度高 ,导通电阻小的特点 .这表明降场电极是一种缓和漂移区掺杂浓度和耐压之间矛盾的有效方法 .该结构是一种器件耐压与导通电阻优化的新途径 .     

场板SOI RESURF LDMOS表面势场分布解析模型

以往对SOI器件的建模基本上基于漂移区全耗尽的假设,且大多未考虑场板对表面势场分布的影响。通过分区求解二维泊松方程,建立了场板SOI RESURF LDMOS表面电势和表面电场分布解析模型。该模型同时考虑了栅场板和漏场板的作用,既适用于漂移区全耗尽的情况,也适用于漂移区不全耗尽的情况。利用此模型和半导体器件仿真工具Silvaco,详细探讨了器件在不同偏压下栅场板和漏场板对漂移区表面电势和电场分布的影响。解析模型结果与数值仿真结果吻合良好,验证了模型的准确性。     

改进击穿电压和导通电阻折中性能的线性变化掺杂漂移区RESURFLDMOS晶体管

本文提出了改进击穿电压和导通电阻折中性能的线性变化掺杂漂移区RESURF LDMOS晶体管新结构.用二维器件软件MEDICI对具有线性变化掺杂漂移区的RESURF LDMOS晶体管的性能进行了数值分析并由实验对其结果进行了验证.结果表明:在相同的漂移区长度下,该新结构较之于优化的常规RESURF LDMOS晶体管,它的击穿电压可由178V提高到234V,增加了1.5倍,而比导通电阻却从7.7mΩ·cm²下降到5mΩ·cm²,减小了30%,显示了很好的击穿电压和导通电阻折中性能.实验结果也证实了数值分析的预言.     

LDMOS漂移区结构优化的模拟

RESURF LDM O S很难兼顾击穿电压和导通电阻对结构的要求。文中采用了D oub le RESURF(双重降低表面电场)新结构,使漂移区更易耗尽。从理论和模拟上验证了D oub le RESURF在漂移区浓度不变时对击穿电压的提高作用以及在保持击穿电压不变的情况下减小导通电阻的效果。同时,在LDM O S结构中加入D oub leRESURF结构也降低了工艺上对精度的要求。为新结构和新工艺的开发研制作前期设计和评估。     

On-State Breakdown Model for High Voltage RESURF LDMOS

An analytical breakdown model under on-state condition for high voltage RESURF LDMOS is proposed.The model considers the drift velocity saturation of carriers and influence of parasitic bipolar transistor.As a result,electric field profile of n-drift in LDMOS at on-state is obtained.Based on this model,the electric SOA of LDMOS can be determined.The analytical results partially fit to our numerical (by MEDICI) and experiment results.This model is an aid to understand the device physics during on-state accurately and it also directs high voltage LDMOS design.     

高压RESURF LDMOS开态击穿模型

建立了高压RESURF LDMOS的开态击穿模型.该模型考虑了载流子的速度饱和现象和寄生双极性晶体管的影响,获得了开态下LDMOS漂移区中的电场分布.基于该模型可以计算出高压 RESURF LDMOS的电学SOA.数值模拟和实验结果部分验证了模型的正确性.该模型有助于深入理解LDMOS开态击穿的物理过程,可用于指导高压LDMOS的设计.     

Unified Breakdown Model of SOI RESURF Device with Uniform/Step/Linear Doping Profile

A unified breakdown model of SOI RESURF device with uniform,step，or linear drift region doping profile is firstly proposed.By the model,the electric field distribution and breakdown voltage are researched in detail for the step numbers from 0 to infinity.The critic electric field as the function of the geometry parameters and doping profile is derived.For the thick film device,linear doping profile can be replaced by a single or two steps doping profile in the drift region due to a considerable uniformly lateral electric field,almost ideal breakdown voltage,and simplified design and fabrication.The availability of the proposed model is verified by the good accordance among the analytical results,numerical simulations,and reported experiments.     

均匀、阶梯和线性掺杂漂移区SOI RESURF器件的统一击穿模型

提出了一个均匀、阶梯和线性掺杂漂移区SOI高压器件的统一击穿模型.基于分区求解二维Poisson方程,得到了不同漂移区杂质分布的横向电场和击穿电压的统一解析表达式.借此模型并对阶梯数从0到无穷时器件结构参数对临界电场和击穿电压的影响进行了深入研究.从理论上揭示了在厚膜SOI器件中用阶梯掺杂取代线性漂移区,不但可以保持较高的耐压,而且降低了设计和工艺难度.解析结果、MEDICI仿真结果和实验结果符合良好.     

有n埋层结构的1200V横向变掺杂双RESURF LDMOS研制

提出有n埋层的横向变掺杂双RESURF 新结构高压LDMOS器件.该结构器件与常规LDMOS相比,采用了相对较薄的外延层,使之与标准CMOS工艺的兼容性得到了改善.基于二维器件仿真软件MEDICI分析了n埋层的浓度、长度和p－降场层的杂质浓度分布对器件耐压的影响,并进行了器件和工艺的优化设计.在国内工艺生产线成功地研制出1200V高压LDMOS,并已用于1200V功率集成电路中.     

Numerical analysis on the LDMOS with a double epi-layer and trench electrodes

We proposed a new lateral double-diffused MOS (LDMOS) structure employing a double p/n epitaxial layer, which is formed on p⁻ substrates. Trenched gate and drain are also employed to obtain uniform and high drift current density. The breakdown voltage and the specific on-resistance of the proposed LDMOS are numerically calculated by using a two-dimensional (2D) device simulator, Medici. The n⁻ drift region and upper p⁻ region of the proposed LDMOS are fully depleted in off-states employing the RESURF technique. The simulation results show that the breakdown voltage is 142 V and specific on-resistance is 183 mΩ mm² when the cell pitch of the LDMOS is 7.5 μm. The proposed LDMOS shows better trade-off characteristics than the previous results.     

漂移区纵向线性掺杂的SOI高压器件研究

随着SOI层厚度的变化,当SOI层的厚度为2μm时,SOI LDMOS器件具有一个最佳的击穿电压.如果漂移区纵向的杂质浓度为线性分布,那么它的纵向电场就会为一个常数,击穿电压会达到最大值,而这种杂质浓度线性分布的漂移区可以通过热扩散得到.采用这种方法制得的SOI LDMOS的纵向击穿电压提高了43%,导通电阻降低了24%,这是因为它的表面浓度更高.