QTAG：静态电流标准监控器的研究进展

为了准备1995年国际测试会议(ITC),质量测试工作组(QTAG)将要正式通过一个静态电流测试(I_(DDQ))的标准监控器。本文说明了QTAG的背景,描述了该工作组在开发和评估新的电流监控器电路时所面临的挑战。本文还提供了几种可能的解决方案。     

晶体管厄利电压对功放电路静态电流影响实例分析

通过对某款功放电路的静态电流随电源电压增加而快速增大的实例,分析了晶体管厄利电压对静态电流变化的影响。通过对同款电路在不同工艺平台中测试结果的对比,分析了静态电流随电源电压变化过快的现象跟晶体管参数厄利电压的相关性,并分析了浅结工艺用于制造功放电路的缺点。分析结果表明通过优化或改变工艺条件(即增加基区结深),使晶体管厄利电压增大,可以解决该款功放电路静态电流随电源电压增大增速过快的问题。     

基于超磁致伸缩材料的FBG电流传感系统北大核心

基于GMM(超磁致伸缩材料)的FBG(光纤布拉格光栅)电流传感器具有光学电流传感器的优点。利用自行配制的环氧树脂胶将FBG与GMM封装为一体作为传感器探头,通过增加偏置磁场改变传感器的静态工作点,采用高频性能良好的铁氧体材料作为导磁回路,约束交变电流产生的磁场并引导进入传感器探头,进而将电流的变化转变成为FBG的波长变化,通过FBG解调系统实现电流测量。通过实验对该传感器的静态和动态响应进行测试,取得了良好的实验结果。     

CMOS集成电路瞬态电流片外电流传感器电路

瞬态电流(IDDT)测试经常被看作是静态电流(IDDQ)测试的替代或补充,特别在深亚微米技术中,受到越来越多的关注。根据一种基于电荷的瞬态电流片外电流传感器电路,并在其基础上进行改进并对两阶多米诺加法器电路进行仿真实验,实验结果表明,改进后的电路能有效读取集成电路中的瞬态电流,从而实现瞬态电流的测试。     

CMOS电路IDDQ测试电路设计

针对CMOS集成电路的故障检测,提出了一种简单的IDDQ静态电流测试方法,并对测试电路进行了设计。所设计的IDDQ电流测试电路对CMOS被测电路进行检测,通过观察测试电路输出的高低电平可知被测电路是否存在物理缺陷。测试电路的核心是电流差分放大电路,其输出一个与被测电路IDDQ电流成正比的输出。测试电路串联在被测电路与地之间,以检测异常的IDDQ电流。测试电路仅用了7个管子和1个反相器,占用面积小,用PSpice进行了晶体管级模拟,实验结果表明了测试电路的有效性。     

一种低静态电流、高稳定性的LDO线性稳压器

该文提出了一种低静态电流、高稳定性低压差(LDO)线性稳压器。LDO中的电流偏置电路产生30nA的低温度漂移偏置电流,可使LDO的静态工作电流降低到4A。另外,通过设计一种新型的动态Miller频率补偿结构使得电路的稳定性与输出电流无关,达到了高稳定性的设计要求。芯片设计基于CSMC公司的0.5m CMOS混合信号模型,并通过了流片验证。测试结果表明,该稳压器的线性调整和负载调整的典型值分别为2mV和14mV;输出的最大电流为300mA;其输出压差在150mA输出电流,3.3V输出电压下为170mV;输出噪声在频率从22Hz到80kHz间为150VRMS。     

三端稳压器测试仪简介

1.综述 GH2911M3三端稳压器测试仪,用于测量各种封装的三端固定、三端可调稳压器的性能参数。主要包括三端稳压器的输出电压V_0,电压调整率Sv,电流调整率Si,静态电流Id,纹波抑制比Sr,静态电流变化量ΔId。测试仪由计算机作为控制机,配备GH2911M3集成稳压器测试单元构成测试系统。测试仪在Window环境下,采用Visual BASIC语言编程,界面友好。测试仪具有多种测量模式供用户选择,方便、快捷、容易掌握。在“常规测试”模式下,用户只需输入被测件型号,仪器将按照国家标准所规定的测量方法对三端稳压器的七个参数逐一测量。测量结果用CRT显示,打印机打印,并按照产品规范判定器件好坏,统计测量数据和合格率。在“自定     

IEC 60950-1(Am.1)2.0中笔记本电脑类产品测试项目探讨

详细介绍IEC 60950-1(Am.1)2.0中笔记本电脑等同类产品的相关测试条款的要求。对标准中输入电流测试、限功率源测试、温升测试及非正常操作测试的测试方法、要点、目的及设计中的规范条款进行解析。分享测试不通过时的整改策略。     

基于电流测试的混合电路故障诊断

在运用小波神经网络进行混合电路故障诊断的过程中,测试参数的选取至关重要。研究了一种基于电流测试的故障诊断。该方法即通过PSPICE模拟电路的静态及动态电流信息,再通过小渡神经网络的结合,证明了该方法在混合电路故障诊断中的可行性,为提高混合电路的故障诊断率提供了一种新的方法。     

手机电流指标测试

手机电流指标测试是对手机的各项电流指标进行精确测试的过程,是评价手机功耗合理与否的重要标准,也是检验手机性能是否达到要求的重要评价指标.该文介绍了手机关机电流测试、睡眠电流测试、平均待机电流测试、通话电流测试和通话峰值电流测试的方法,并以奥克斯V989为例,对手机电流指标进行测试并分析,从而对手机性能进行评价.     

Fault detection in CMOS/SOI mixed-signal circuits using the quiescent current test

Main stream bulk CMOS and the variants of silicon-on-insulator (SOI) CMOS technologies are discussed with respect to testing for the quiescent current of mixed-signal integrated SOI circuits. The 2–3 times lower static power consumption in fully depleted CMOS/SOI compared to bulk CMOS allows quiescent current testing also for high performance analogue circuits at an acceptable defect resolutions. From first simulations and technological considerations, it turned out that quiescent current tests are able to detect not only commonly known defects, but also SOI specific defects such as self-heating, kink-effect or the parasitic bipolar behaviour. It is further shown that in partially depleted thick-film SOI, the kink-effect and parasitic bipolar transistor support the quiescent current test for some specific defects as they elevate the defective quiescent current level. In fully depleted kink-free SOI circuits, the kink-effect may occur due to process failures but then can be detected by quiescent current tests. A special fault simulation model for the kink-effect is presented. The I_ccq test technique is studied for a CMOS/SOI Miller operational amplifier. Normal 6-σ variation of the aspect ratio and the threshold voltage do not jeopardise the defect detection in the quiescent current. First, results confirm the good detection capabilities of the quiescent current test, in particular, of failures which are not visible in the output voltage.     

一种超低静态电流LDO线性稳压器的设计

为了延长便携式、可穿戴医疗设备的待机时间,设计了一种具有超低静态电流的低压差(LDO)线性稳压器。采用误差放大器与基准电路相结合的结构,在降低静态电流的同时减小芯片面积;其次,利用负载检测模块,降低了空载及轻载时过温保护和过流保护等模块的静态电流。采用自适应偏置电流技术来动态调整稳压环路各支路的工作电流以及零点频率补偿方式,解决了静态功耗与瞬态响应和环路带宽间的矛盾。该LDO线性稳压器采用0.35μm CMOS工艺进行流片加工,测试结果表明,该LDO线性稳压器静态电流为700 nA,最大负载电流为150 mA,轻载与满载跳变时上过冲电压为63 mV,下过冲电压为55 mV。     

锂离子电池热滥用试验研究

探究锂离子电池在过热条件下的安全问题;分析现行标准中的热滥用试验的试验条件和试验方法。试验研究了热滥用试验中的高温保持时间和试验温度;最后提出对现行锂离子电池热滥用试验的改进建议。     

IEC61000-3-12标准的分析与应用

为限制非线性负荷向电网发射的谐波电流，截止目前，共计颁布了两个关于谐波电流限制的国际标准，即IEC61000—3-2：2000和IEC61000—3—12：2005。为了更好地理解这两个标准，本文对这两个标准进行了详细比较，包括基本概念、适用范围等方面，熏点描述和分析了后者中新增的一些概念和物理意义，为了标准的理解与具体应用打下基础。针对单相低压交流电源供电的家用柜机变频空调的谐波电流抑制问题，为了适合IEC61000—3—12：2005，给出了两种输入功率6．6kW的单相完全有源模拟和数字PFC的具体设计和谐波电流测试结果。     

Built-in current sensor for /spl Delta/I/sub DDQ/ testing

This paper presents the implementation of a built-in current sensor for /spl Delta/I/sub DDQ/ testing. In contrast to conventional built-in current monitors, this implementation has three distinctive features: 1) built-in self-calibration to the process corner in which the circuit under test was fabricated; 2) digital encoding of the quiescent current of the circuit under test for robustness purposes; and 3) enabling versatile testing strategy through the implementation of two advanced /spl Delta/I/sub DDQ/ testing algorithms. The monitor has been manufactured in a 0.18-/spl mu/m CMOS technology and it is based on the principle of disconnecting the device under test from the power supply during the testing phase. The monitor has a resolution of 1 /spl mu/A for a background current less than 100 /spl mu/A or 1% of background currents over 100 /spl mu/A to a total of 1-mA full scale. The sensor operates at a maximum clock speed of 250 MHz. The quiescent current is indirectly determined by counting a number of clock pulses which occur during the time the voltage at the disconnected node drops below a reference voltage value. Basically, at the end of the count period, the counted value is inversely proportional to the quiescent current of the device under test. Then, a /spl Delta/I/sub DDQ/ unit processes the counted number and the outcome is compared with a reference number to determine whether a defect exists in the device under test. Accuracy is improved by adjusting the value of the reference number and the frequency of the clock signal depending upon the particular process corner of the circuit under test. The monitor has been verified in a test chip consisting of one "DSP-like" circuit of about 250,000 transistors. Experimental results prove the usefulness of our approach as a quick and effective means for detecting defects.     

一种面向单片DC/DC的低压高效片上电流检测技术

本文提出并实现了一种面向电流模式单片开关DC/DC转换器的低压高效片上电流采样电路.该电路利用功率管等效电阻电流检测技术和无需OP放大器的源极输入差分电压放大技术,使电路的应用范围可低达2.3V;-3dB带宽12MHz;在最大负载电流情况下的静态电流峰值仅19μA,比常规采用功率管镜像电流检测技术的静态电流峰值低1.5个量级左右.转换器基于0.5μm 2P3M Mixed Signal CMOS工艺设计制作.测试结果表明,电流检测电路的最大检测电流1.1A,转换器的输入最低电压2.3V,重负载转换效率高于93%.     

High-gain wideband error amplifier topology for DC-DC buck converter switching at 20 MHz

A wideband error amplifier topology with increased DC-gain and reduced quiescent current consumption is presented. The reduction in quiescent current consumption is achieved by lowering the output stage current, which helps to increase the output impedance and hence the overall DC-gain of the amplifier. Simulation results show that the proposed topology has 60 dB DC gain and 540 MHz unity gain bandwidth with 450 muA quiescent current consumption. The experimental result of the loop-gain of a high-frequency (20 MHz) DC-DC buck converter that utilises the proposed topology also confirms the simulation results.     

一种适合于开关稳压器的新颖电流检测方法

针对开关稳压器中负载电流检测难以同时做到准确、同步和结构简单这一难题,结合自己多年工作经验,提出了一种新颖的开关稳压器负载电流检测的新方法。其基本原理是利用断续模式（DCM）下负载电流与同步管栅极驱动信号N_DRV的同步关系,通过检测该栅极信号来检测开关稳压器的输出负载电流。这种方法不仅使负载电流检测同步和准确,且同时克服检测电感平均电流带来的电路结构复杂及实现上的困难。该电路经过HSpice仿真验证,其仅消耗5μA的静态电流,工作状态良好。     

Off-chip Iddq monitor with standard test interface

Off-chip current testing is being considered as an efficient mechanism for improving the quality of electronic systems at the printed circuit board level. This well known fact is linked with the industry accepted testing interface standard IEEE P1149.1 (`Standard test access port and boundary-scan architecture'). A specific integrated circuit with the capability of concurrently measuring the quiescent current level for two integrated circuits under test (ICCUT) is presented with its basis. Architecture and implementation details. All the functions of the monitors are accessible via the standard test access port     

Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor

This paper presents a test method based on the analysis of the dynamic power supply current, both quiescent and transient, of the circuit under test. In an off-chip measurement, the global interconnect impedance associated with the chip package and the test equipment and, also, the chip input/output cells will complicate the extraction of the information provided by the current waveform of the circuit under test. Thus, the supply current is measured on-chip by a built-in current sensor integrated in the die itself. To avoid the effective reduction of the voltage supply, the measurement is performed in parallel by replicating the current that flows through selected branches of the analog circuit. With the aim of reducing the test equipment requirements, the built-in current sensor output generates digital level pulses whose width is related to the amplitude and duration of the circuit current transients. In this way the defective circuit is exposed by comparing the digital signature of the circuit under test with the expected one for the fault-free circuit. A fault evaluation has been carried out to check the efficiency of the proposed test method. It uses a fault model that considers catastrophic and parametric faults at transistor level. Two benchmark circuits have been fabricated to experimentally verify the defect detection by the built-in current sensor. One is an operational amplifier; the other is a structure of switched current cells that belongs to an analog-to-digital converter.