RX64DTH -a fully integrated 64-channel ASIC for a digital X-ray imaging system with energy window selection

We report on the multichannel IC (RX64DTH) designed for position sensitive X-ray measurements with silicon strip detectors and dedicated to medical imaging applications. This integrated circuit has a binary readout architecture with a double threshold allowing on selection energy window for measured signals. The design was realized in a 0.8 /spl mu/m CMOS process. The core of the RX64DTH IC consists of 64 readout channels. The single channel is built with four basic blocks: charge sensitive preamplifier, shaper, two independent discriminators, and two independent 20-bit counters. Each readout channel counts pulses which are above the low discriminator threshold and counts pulses independently above the high discriminator threshold. The energy resolution in such architecture is limited by the noise of a single channel and by channel to channel threshold spread. We present the noise and matching performance of a 384-channel module built with a silicon strip detector and six RX64DTH ICs. In the 384-channel module an equivalent noise charge of about 200 el. rms is achieved for the shaper peaking time of 0.8 /spl mu/s and strip capacitance of 3 pF. The deviation of discriminator thresholds for the whole system is only 87 el. rms. The obtained results show that the energy resolution and uniformity of analog parameters (noise, gain, offset) are sufficient for medical diagnostic applications such as dual energy mammography and angiography.     

基于3D Si PIN阵列热中子探测器的变增益宽动态前端读出电子学设计

基于Si CMOS技术的前端读出ASIC主要是根据3D Si PIN阵列热中子探测器的输出信号特性设计的。所设计的读出ASIC的主要电路模块包括电荷灵敏放大器（CSA）、模拟开关设计、具有三级电荷灵敏自动转换的自动增益控制模块（AGC）、相关双采样（CDS）和基准电流源电路。仿真结果表明,前端电路的输入动态范围为10 fC~80 pC。根据热中子探测器输出信号特性设计的ASIC的3个增益系数分别为19 V/pC、039 V/pC和94 mV/pC。所设计的ASIC的积分非线性小于 1%。单通道静态功耗约为 536 mW。零输入探测器电容时的等效噪声电荷为2416e-。计数率可达1 MHz 。     

ASIC With Multiple Energy Discrimination for High-Rate Photon Counting Applications

An ASIC for high rate photon counting measurements with multiple energy discrimination is presented. Optimized for pixelated CdZnTe sensors, the ASIC is composed of 64 channels with low-noise charge preamplification, high-order shaping (40 ns minimum peaking time), and five window-discriminators with associated 16-bit counters. An efficient readout scheme allows simultaneous measurement and readout through a 60 MHz 16-bit output bus. The ASIC architecture and experimental results are reported, and the impact of the shaper order on the resolution, ballistic deficit, and pile-up is discussed     

A 64-Channel Wide Dynamic Range Charge Measurement ASIC for Strip and Pixel Ionization Detectors

In this paper we report a 64-channel application specified integrated circuit (ASIC) for the readout of parallel plate strip and pixel ionization detectors. The detectors measure the intensity and the geometrical characteristics of a hadron beam for hadrontherapy cancer treatments. The ASIC is based on a current to frequency converter followed by a counter. It uses a charge balancing integration technique to obtain a dynamic range in excess of$10^5$with a nonlinearity of less than 1%. The ASIC has been designed in a CMOS 0.8$mu m$technology and it has been used for the readout of both strip ionization detectors for beam calibration and pixel detectors for beam monitoring during treatment. A new version of the chip in CMOS 0.35$mu m$technology which allows bipolar input currents has been designed and is currently under test.     

A QTC-based signal readout for position-sensitive multi-output detectors

A new signal readout method for position-sensitive multi-output detectors,such as those in high-energy spectroscopy measurement and nuclear imaging,was developed by combining the charge division circuit,summing circuit and charge-to-time conversion(QTC) circuit.The 64 outputs of a Hamamatsu H8500 position-sensitive photomultiplier tube were processed,and three digital pulses were generated.The widths of digital pulses were determined using the time-to-digital converter in an field programmable gate array.The energy and position information of incident y-rays is estimated based on the proportionality between the width of digital pulses and input charge created by y-photons.A prototype was built using discrete components and tested,and the energy and position resolutions were improved compared with that obtained with standard ADCs.This method greatly simplifies the front-end electronics and the digital interface.It enables a compact electronics system and an easy integration into an ASIC.     

A versatile 16-channel front-end integrated circuit for semiconductor radiation detectors

A CMOS front-end integrated circuit consisting of 16 identical analog channels is proposed for semiconductor radiation detectors. Each of the 16 channels has a low noise charge sensitive amplifier, a pulse shaper, a peak detect and hold circuit and a discriminator, while analog voltage and channel address are routed off the chip. It can accommodate both electron and hole collection with selectable gain and peaking time. Sequential and sparse readout, combining with self-trigger and external trigger, makes four readout modes. The circuit is implemented in a 0.35 μm DP4M (double-poly-quad-metal) CMOS technology with an area of 2.5×1.54 mm2 and power dissipation of 60 mW. A single channel chip is tested with Verigy 93000. The gain is adjustable from 13 to 130 mV·fC–1 while the peaking time varies between 0.7 and 1.6 μs. The linearity is more than 99% and the equivalent noise charge is about 600e.     

Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.     

半导体阵列微剂量探测器前端读出电路设计

根据三维Si SOI PIN像素微剂量探测器特性参数,设计了一种基于GF chrt018IC CMOS工艺的前端读出电路。该读出电路主要包括PMOS输入的电荷灵敏前前置放大器,有源整形滤波电路,电压比较器及基准电流源等,可实现对微剂量信号的放大、滤波降噪、甄别输出等功能。仿真测试表明:能量探测范围为5~500 fC,单通道功耗约为2 mW,总噪声性能为0.05 f C+1.6×10~(-3)fC/pF。     

Initial Beam Test Results from a Silicon-Strip Detector with VLSI Readout

Silicon detectors with 256 strips, having a pitch of 25 ?m, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 ?m and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 ?m were cleanly resolved.     

Application of CMOS charge-sensitive preamplifier in triple-GEM detector

1 Introduction With novel materials and advanced technique of printed circuit board (PCB) and micro-electronics be- ing used in MPGD, over the past two decades, great progress has been made in MPGD[1], and as a new type of MPGD, the GEM[2] detector was developed during the late 1990s. Standard GEM from CERN is a thin, two-side copper-coated Kapton foil, perforated with a high density of holes etched using a photolitho- graphic process. The diameter of these holes is about 70 μm (ext…     

GERO: a general SCA-based readout ASIC for micro-pattern gas detectors with configurable storage depth and on-chip digitizer

The paper presents GEneral Read Out(GERO), a general readout ASIC based on a switched capacitor array for micro-pattern gas detectors. It aims at providing general readout electronics for low-to-medium event-rate gas detectors with high sampling frequency, configurable storage depth, and data digitalization. The first prototype GERO chip integrates 16 channels and was fabricated using a 0.18-lm CMOS process. Each channel consists of a sampling array working in a ping-pong mode, a storage array with a 1024-cell depth, and 32 Wilkinson analog-todigital converters. The detailed design and test results are presented in the paper.     

CMOS low-noise switched charge sensitive preamplifier for CdTe andCdZnTe X-ray detectors

CdTe and CdZnTe X-ray detector arrays for imaging and spectroscopy provide low capacitance current sources with low leakage currents. The optimal shaping time for low-noise operation is relatively high in CMOS analog channels that provide the readout for these detectors. The shaper is centered at lower frequencies, and thus the 1/f noise from the electronics is the main noise source that limits the resolution of the channel. The optimal dimensions of the input stage MOSFET are determined by this noise. In this paper a design criterion for the optimization of the resolution and the power consumption in a 1/f noise dominated readout is introduced. A readout based on CMOS switched charge sensitive preamplifier without feedback resistor has been designed and fabricated in the CMOS 2-μ low-noise analog process provided by MOSIS. This design provides high sensitivity and the possibility to integrate a large number of channels with low power consumption. Measurements of the performance of a first prototype chip are presented     

Counting and Integrating Readout for Direct Conversion X-ray Imaging: Concept, Realization and First Prototype Measurements

A novel signal processing concept for X-ray imaging with directly converting pixelated semiconductor sensors is presented. The novelty of this approach compared to existing concepts is the combination of charge integration and photon counting in every single pixel. Simultaneous operation of both signal processing chains extends the dynamic range beyond the limits of the individual schemes and allows determination of the mean photon energy. Medical applications such as X-ray computed tomography can benefit from this additional spectral information through improved contrast and the ability to determine the hardening of the tube spectrum due to attenuation by the scanned object. A prototype chip in 0.35-micrometer technology has been successfully tested. The pixel electronics are designed using a low-swing differential current mode logic. Key element is a configurable feedback circuit for the charge sensitive amplifier which provides continuous reset, leakage current compensation and replicates the input signal for the integrator. This paper will discuss measurement results of the prototype structures and give details on the circuit design     

Low-Power Amplifier-Discriminators for High Time Resolution Detection

Low-power amplifier-discriminators based on a so-called NINO architecture have been developed with high time resolution for the readout of radiation detectors. Two different circuits were integrated in the NINO13 chip, processed in IBM 130 nm CMOS technology. The LCO version (Low Capacitance and consumption Optimization) was designed for potential use as front-end electronics in the Gigatracker of the NA62 experiment at CERN. It was developed as pixel readout for solid-state pixel detectors to permit minimum ionizing particle detection with less than 180 ps rms resolution per pixel on the output pulse, for power consumption below 300 muW per pixel. The HCO version (High Capacitance Optimization) was designed with 4 mW power consumption per channel to provide timing resolution below 20 ps rms on the output pulse, for charges above 10 fC. Results presented show the potential of the LCO and HCO circuits for the precise timing readout of solid-state detectors, vacuum tubes or gas detectors, for applications in high energy physics, bio-technologies or medical imaging.     

DAMPE-PSD读出电子学研制

暗物质粒子探测卫星(dark matter particle explorer, DAMPE)是我国空间科学卫星系列的首发星,用于找出可能的暗物质粒子信号。塑料闪烁体阵列探测器(plastic scintillator detector, PSD)分系统作为卫星有效载荷的主体部件之一,参与承担高能粒子电荷测量和电子/γ射线鉴别任务。PSD由82根塑料闪烁体条和164个光电倍增管（photomultiplier tube, PMT)组成,有328个输出通道,每根塑料闪烁体条的动态范围为2×103,需配备1套完备的读出电子学系统。该电子学系统由4块前端电子学（front-end electronics, FEE）板构成,共具有360个信号处理通道,总功耗6 W。电路主要包括电荷测量电路、模拟调理电路、模数变换电路、刻度电路、环境监测电路、FPGA电路、电源管理电路以及接口电路等,其主要功能是基于32路模拟信号将PMT的电荷信号输入VA160 ASIC芯片,考虑了抗辐照加固、温度设计等一系列关键问题,以确保在严酷的太空中具有长期的可靠性。测试结果表明,该FEE系统工作稳定、性能良好,具有较好的技术指标,每个电子学通道实现了0～12.5 pC的动态范围,通道的随机噪声水平好于2 fC,积分非线性好于0.6%。FEE能适应恶劣的空间环境,具有很高的可靠性。FEE配合PSD样机还分别于2014年和2015年在欧洲核子中心（CERN）的PS和SPS终端成功完成了2次束流试验,验证了PSD的探测能力完全满足任务书中提出的功能和指标要求,能很好实现实际科学任务需求。     

远距离大动态范围电荷测量电路的设计

介绍了大型高海拔空气簇射观测站(Large High Altitude Air Shower Observatory,LHAASO)空气簇射芯探测器阵列(Shower core detector array,SCDA)读出电子学方案的预研设计。系统采用基于电荷积分法的电荷测量方案,读出电子学通过同轴电缆接收光电倍增管输出的电流信号;采用在输入端与电荷积分放大器的虚地点之间接入等效50?电阻的终端阻抗匹配方案,并通过Pspice仿真验证该阻抗匹配的可行性。电路测试结果表明,该电路能满足远距离10 bit大动态范围电荷测量的设计指标要求。     

Characteristics of 16-Channel ASIC Preamplifier Board for Microstrip Gas Chamber and Animal PET

A 16-channel ASIC preamplifier board has been designed for microstrip gas chamber (MSGC) and animal position emission tomography (PET) detectors. The highly integrated ASIC chips can be used for individual readouts from a large number of channels to improve the spatial resolution and counting rate. The preamplifier board was tested to have a low optimum equivalent noise charge (ENC) of ~ 1400 e^? FWHM at a shaping time of 0.1 μs. The output voltage to input charge gain is 0.96 V/pC, and the nonlinearity is ~ 2:0% over a range of ?500 fC to 1000 fC in input charge. The rise time (10%–90%) with no input capacitor is about 54 ns. The power consumption of this preamplifier board is ~ 100 mW. The preamplifier board has been used to read out a 3 × 3 cm MSGC plate and an optimum FWHM energy resolution of 19.1% (5.9 keV peak of Fe-55) was obtained.     

双面硅条探测器读出系统设计

双面硅条探测器(DSSD)用于实现中国电磁监测试验卫星高能粒子探测器载荷的望远镜系统。为了实现DSSD读出电子学低功耗、高集成度的要求,设计了一种基于ASIC VA64TA2的电子学读出系统,使用²⁴¹Am 5.486 MeV α源对DSSD读出系统进行了测试。DSSD探测器结面分辨率为1%~2%,欧姆面分辨率为3%~4%,达到了探测器额定性能。     

CsI(Tl)闪烁探测器读出电路设计

介绍了配置于新型γ能谱仪的CsI(Tl)闪烁探测器的读出电路设计。输入缓冲级采用折叠嵌位电路,改善了系统频率特性并提高了输入阻抗;放大级采用自举电路,改善了系统动态性能并提高了开环增益;输出级采用电流源负载电路,改善了输出信号的线性度并增强了系统的稳定性。实验表明:读出电路噪声为51.08 f C+1.97 f C/p F,时间漂移为0.112%,探头对137Cs源γ射线的输出信号信噪比可达23:1,能量分辨率可达4.98%。     

适用于高计数率下的放大甄别一体化电路

介绍一种由电荷灵敏前置放大器、主放大器、甄别器、成形电路所组成的一体化电路.该仪器主要用于高计数测量中,最高计数率可达106/s,它主要适应于高灵敏度的3He中子探测器,同时也可以用于其他重离子探测器,该仪器的输出脉冲可直接与CMOS或TTL逻辑电平兼容.它有功耗低,体积小,灵敏度高,便于野外使用等特点.