Deduction, Strategies, and Rewriting

Automated deduction methods should be specified not procedurally, but declaratively, as inference systems which are proved correct regardless of implementation details. Then, different algorithms to implement a given inference system should be specified as strategies to apply the inference rules. The inference rules themselves can be naturally specified as (possibly conditional) rewrite rules. Using a high-performance rewriting language implementation and a strategy language to guide rewriting computations, we can obtain in a modular way implementations of both the inference rules of automated deduction procedures and of algorithms controling their application. This paper presents the design of a strategy language for the Maude rewriting language that supports this modular decomposition: inference systems are specified in system modules, and strategies in strategy modules. We give a set-theoretic semantics for this strategy language, present its different combinators, illustrate its main ideas with several examples, and describe both a reflective prototype in Maude and an ongoing C++ implementation.     

Invariant-driven specifications in Maude

This work presents a general mechanism for executing specifications that comply with given invariants, which may be expressed in different formalisms and logics. We exploit Maude’s reflective capabilities and its properties as a general semantic framework to provide a generic strategy that allows us to execute Maude specifications taking into account user-defined invariants. The strategy is parameterized by the invariants and by the logic in which such invariants are expressed. We experiment with different logics, providing examples for propositional logic, (finite future time) linear temporal logic and metric temporal logic.     

Synchronous set relations in rewriting logic

This paper presents a mathematical foundation and a rewriting logic infrastructure for the execution and property verification of synchronous set relations. The mathematical foundation is given in the language of abstract set relations. The infrastructure, which is written in the Maude system, enables the synchronous execution of a set relation provided by the user. By using the infrastructure, algorithm verification techniques such as reachability analysis and model checking, already available in Maude for traditional asynchronous rewriting, are automatically available to synchronous set rewriting. In this way, set-based synchronous languages and systems such as those built from agents, components, or objects can be naturally specified and simulated, and are also amenable to formal verification in the Maude system. The use of the infrastructure and some of its Maude-based verification capabilities are illustrated with an executable operational semantics of the Plan Execution Interchange Language (PLEXIL), a synchronous language developed by NASA to support autonomous spacecraft operations.     

Taming distributed system complexity through formal patterns

Many distributed systems are real-time, safety-critical systems with strong qualitative and quantitative formal requirements. They often need to be reflective and adaptive, and may be probabilistic in their algorithms and/or their operating environments. All this makes these systems quite complex and therefore hard to design, build and verify. To tame such system complexity, this paper proposes formal patterns, that is, formally specified solutions to frequently occurring distributed system problems that are generic, executable, and come with strong formal guarantees. The semantics of such patterns as theory transformations in rewriting logic is explained; and a representative collection of useful patterns is presented to ground all the key concepts and show their effectiveness.     

Applying formal verification to the AAMP5 microprocessor: A case study in the industrial use of formal methods

Formal specification combined with mechanical verification is a promising approach for achieving the extremely high levels of assurance required of safety-critical digital systems. However, many questions remain regarding their use in practice: Can these techniques scale up to industrial systems, where are they likely to be useful, and how should industry go about incorporating them into practice? This paper discusses a project undertaken to answer some of these questions, the formal verification of the microcode in the AAMP5 microprocessor. This project consisted of formally specifying in the PVS language a Rockwell proprietary microprocessor at both the instruction-set and register-transfer levels and using the PVS theorem prover to show the microcode correctly implemented the instruction-level specification for a representative subset of instructions. Notable aspects of this project include the use of a formal specification language by practicing hardware and software engineers, the integration of traditional inspections with formal specifications, and the use of a mechanical theorem prover to verify a portion of a commercial, pipelined microprocessor that was not explicitly designed for formal verification.     

Programmed Strategies for Program Verification

Plover is an automated property-verifier for Haskell programs that has been under development for the past three years as a component of the Programatica project. In Programatica, predicate definitions and property assertions written in P-logic, a programming logic for Haskell, can be embedded in the text of a Haskell program module. Properties refine the type system of Haskell but cannot be verified by type-checking alone; a more powerful logical verifier is needed.Plover codes the proof rules of P-logic, and additionally, embeds strategies and decision procedures for their application and discharge. It integrates a reduction system that implements a rewriting semantics for Haskell terms with a congruence-closure algorithm that supports reasoning with equality. It employs strategies such as structure splitting and case analysis to explore alternative valuations of expressions of type Bool or other finite data types, but these strategies can lead to exponential growth of terms and must be employed cautiously.Plover itself is written in Stratego, which has proven to be a powerful language tool for implementating a verifier. We discuss the design and implementation of some strategies that enable Plover to comprehend Haskell and verify many valid property assertions.     

基于LonWorks技术双处理器结构的模拟量输出节点AO研究

目前大多数Lon节点只具有单一的神经元处理器,其控制能力不高.针对这一现状,利用LonWorks技术原理介绍了基于神经元芯片MC143150和单片机AT89S51双处理器结构模拟量输出节点AO的测控单元设计,通讯单元设计,两处理器接口设计,软件编程以及节点的抗干扰措施、节点性能的优化方法.     

CAN总线控制器IP核设计实现

CAN总线是一种成熟的串行通信总线,它具有可靠性高、稳定性好、抗干扰能力强、通信速率高、维护成本低、实时性强、很好的开放性及数据兼容性等优点。CAN总线这些众多的优点使其广泛应用于工业自动化控制等领域。其应用的广泛性则进一步对CAN总线IP提出了需求。同时以IP实现的CAN总线控制器所具有的通用处理器访问接口,良好的可移植性等优点使其可以集成于各种嵌入式SoC设计中。文中从CAN总线的规范和特点出发,提出了CAN总线控制器IP核的特点并定义了其功能,采用Verilog语言设计实现了CAN总线控制器IP核的功能,最后通过仿真和FPGA原型验证,证明了设计实现的正确性。目前CAN总线控制器IP核已经应用于SOPC和SoC的嵌入式应用设计中。     

CTL-property Transformations along an Incremental Design Process

This paper formalizes an incremental approach to design flow-control oriented hardware devices described by Moore machines. The method is based on successive additions of new behaviours to a simple device in order to build a more complex one. The new behaviours added must not override the previous ones. A set of CTL formulae is assigned to each step of the design. The links between the formulae of two consecutive design steps are formalized as a set of formula-transformations F, stating that: for all CTL formula f with atomic propositions related to step i, f is satisfied on a design at step i, iff F(f) is satisfied on the design extended at step i + 1. This result extends the classical CTL property preservation results in a particular context. Moreover, it simplifies the writing of properties for a new device. This approach has been applied in the design of bus protocol converters and the transformations were useful to perform non-regression analysis. It could also be applied in order to simplify both system and formulae in particular cases.     

一种分解演化的电路自动设计方法①

提出一种并行递归分解算法,它有规律地将待演化电路逐步分解直到设计成功,整个过程无需人工干预,提高了电路设计的自动化程度。该算法将目标电路的演化设计过程转化为其多个子电路的并行演化过程,并利用＂特长个体＂的互补性提高搜索效率。实验表明,该分解策略能有效提高演化逻辑电路的设计效率和成功率。     

Formal Design of Cache Memory Protocols in IBM

We describe the formal design techniques currently used in IBM to develop cache protocol controllers for high-end servers. In our approach to formal design, formal specification and verification methods are incorporated into the hardware design process, starting from the earliest stages of a hardware project. We describe collaborations between a formal methods expert and hardware designers on two high performance server projects. Properties of the design are verified using both manual proof techniques and model checking. We discuss the modelling and model checking techniques we have developed and indicate future directions.     

A novel formal verification approach for RTL hardware IP cores

We present a promising formal verification methodology based on the inductive approach using the imPROVE-HDL tool. This methodology is dedicated for RTL IPs or IP-based digital/logic hardware designs to prove the correctness of their temporal properties related to the control-dominated architecture model. Each temporal property can be checked through the IP interface where all properties have to be proved or disproved. We developed a new methodology to generate the appropriate environment of the IP interface according to the design context (master, slave, arbiter and decoder) before starting the verification of all properties one by one. When all temporal properties are verified, we generate some test sequences that contain a complex scenario to check the compatibility between all properties. We implemented our methodology to generate the appropriate environment and applied the inductive approach to verify various properties of two real IP designs using the imPROVE-HDL tool developed by TNI-Valiosys. The first design is an RTL IP-based digital hardware dedicated for real time video processing, where the second one performs an AHB to AHB Bridge. On these designs, we successfully proved few properties and discovered a design violation.     

Integration of Hardware and Software Platforms in Creating Manufacturing Computer Systems

An approach to the choice of an optimum combination of hardware and software platforms as a basis of a computer system is proposed. The procedures of choice and estimation criteria proposed are oriented towards the implementation in the form of a "business logic" algorithm embedded into an interactive information support system.     

家居环境无线网络监控系统

随着家居环境无线网络监控系统技术的不断完善,家居环境无线网络监控系统的市场需求越来越大本文详细介绍了家居环境无线网络监控系统的结构、软硬件设计过程以及重要的技术挑战,最后对家居环境无线网络监控系统的发展趋势进行了展望。     

高等学校思想政治教育柔性管理理论依据及策略

随着大学生思想政治教育的不断深入发展,柔性管理理论以其符合中国优秀传统思想文化、西方进步思想文化、马克思主义 理论和中国共产党执政理念,得到高等学校思想政治教育工作者的重视。高等学校思想政治教育工作实施柔性管理存在其理念未 能彻底贯彻实行、未能充分实现大学生自主管理以及缺乏对大学生心理健康的关怀等不足,为此,要采取刚柔相济、实现大学生自 主管理、加强心理健康管理和完善激励机制等策略,促进高等学校思想政治教育工作的健康发展。     

飞行器系统级BIT设计与验证技术

为解决飞行器系统在设计集成与验证阶段机内测试(BIT)的设计技术与能力验证的通用技术性问题,从分析国外BIT发展趋势、最新技术以及飞行器系统故障发生特点和现状入手,提出了飞行器系统BIT设计的通用技术方法与工程流程,分析了系统运行与故障活动的参数表征、逻辑关系,提出了系统BIT综合设计技术、建模方法以及故障验证的原理方法.通过对典型实例系统初步探索,构建了相应功能故障模型和验证控制参数,应用表明本方法具有工程实用性.     

PLC在自动供水系统中的应用

城市供水逐渐向自动化、恒压供水的趋势发展,基于此,该文对自动恒压供水系统进行了研究与设计,从自动恒压供水的基本原理切入进行了分析,同时在完成了硬件选型的基础上,重点进行了自动恒压供水系统的设计,探讨了西门子PLC在自动恒压供水系统中的应用,给出了系统的硬件设计和软件流程设计,对于进一步提高供水系统的自动化应用水平具有一定借鉴意义。