Impact of laser intensity noise on ASK two-port optical homodyne receivers

The letter describes initial experimental results obtained with a multiport optical homodyne receiver employing a DFB laser. The receiver performance is found to be limited by the intensity noise of the local oscillator rather than by the phase noise, even when the product of the IF linewidth and the bit duration is as large as 0.56. A relative intensity noise level of at least ? 140dB/Hz will be required for a satisfactory receiver performance with ? 15dBm local oscillator power.     

Complementary BAW oscillator for ultra-low power consumption and low phase noise

A complementary cross coupled BAW parallel resonance oscillator offering ultra-low power consumption and a good phase noise performance is presented. The power consumption in this structure is 50?% less than the classical NMOS based structure without any penalty in the phase noise performance. Rather, this structure serves to reduce the noise contribution of the biasing transistors at the output leading to a marginal improvement in thermal noise performance as compared to the NMOS based structure. Furthermore, the flicker noise upconversion of this complementary structure can be minimized by proper design considerations. The power consumption in case of such a complementary structure based oscillator (designed in 180nm CMOS process) employing a 2.497?GHz BAW resonator is around 675???W for an amplitude of 300?mV with a phase noise of ?140?dBc/Hz at 1?MHz offset.     

面向空间引力波探测的低噪声平衡零拍探测系统研究（特邀）

空间引力波探测频段位于0.1 mHz~1 Hz范围内,在该频段内包含了更大特征质量和尺度的引力波波源信息。目前,基于不同尺寸及空间轨道的大型激光干涉空间引力波探测计划已经逐步实施,其中在干涉仪的激光光源系统中,需要抑制激光强度噪声及频率噪声等,光电探测作为激光噪声表征及抑制的第一级器件,其性能将直接影响激光噪声抑制效果。通过选定低噪声芯片、高稳定偏压系统的基础上,采用自减电路及跨阻放大电路进行整体电路设计;在电磁屏蔽、低温漂系数元件、低噪声供电以及主动温控等技术手段实现了高增益低噪声平衡零拍探测系统的研制;结合快速傅里叶变换法以及对数轴功率谱密度算法对其增益、带宽等性能进行评估测试,并进一步对激光的强度噪声在0.05 mHz~1 Hz频段进行探测表征。实验结果表明:所研发平衡零拍探测电子学噪声谱密度在1 mHz~1 Hz的频率范围内在3.6×10?5 V/Hz1/2以下,小于空间引力波探测对激光光源噪声要求;进一步当入射光功率为400 μW时,测量得到平衡零拍探测系统在0.1 mHz~1 Hz的频率范围内增益在20 dB以上;激光强度噪声谱密度在1 mHz处为3.6×10?2 V/Hz1/2,实现低噪声光电探测及激光强度噪声表征,为空间引力波探测中激光强度噪声表征及抑制等方面提供关键器件支撑。     

Low frequency noise physical analysis for the improvement of the spectral purity of GaAs FETs oscillators

Low frequency (L.F.) noise in GaAs FETs was investigated both theoretically and experimentally. The main contribution to the overall noise at frequencies over 10³ Hz was found to be flicker noise generated in the gradual region of the channel.A new simple relationship is proposed to derive the noise voltage intensity referred back to the input at normal operating conditions: it is reported that this noise spectral intensity does not depend on bias voltages for micrometer or submicrometer devices. This relationship provides a fast and easy way for assessing devices for their L.F. noise: an improvement in the spectral purity of GaAs FETs oscillators designed with low L.F. noise FETs is reported.     

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

We present an integrated fractional-N low-noise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is ?87 dBc/Hz and ?106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to ?98 dBc/Hz at 10 kHz and ?111 dBc/Hz at 1 MHz offset, respectively, were measured.     

Dual-band low-phase-noise LC-QVCO using series coupling and switched biasing techniques

An LC-tank quadrature voltage-controlled oscillator (QVCO) is proposed to achieve frequency-band reconfigurability and low phase noise. In this work, phase noise contributed by the 1/f noise of coupling transistors and tail transistors is noticeably reduced when series coupling and switched biasing techniques are simultaneously adopted. The proposed QVCO was implemented in 0.25-μm triple-well CMOS process for K-PCS and WCDMA bands. Measured results showed a phase noise of ?117 dBc/Hz at an offset of 1 MHz and a phase-noise figure-of-merit of ?172 dBc/Hz while consuming 8.13 mA from a 2-V power supply.     

Quasi-planar K-band push-push low phase noise oscillator stabilized by cavity resonator

The results of developing a K-band (24 GHz) push-push low phase noise transistor oscillator have been presented. This oscillator is stabilized by a rectangular resonant metallic cavity. The power level of output signal is ?9.5 dBm, the fundamental harmonic suppression is 21 dB. Single sideband (SSB) phase noise spectral density of ?98 dBc/Hz at 10 kHz and ?128 dBc/Hz at 100 kHz offset from the carrier frequency is at the level of dielectric resonator oscillators (DRO) scaled to the same frequency. The oscillator features a compact size, low cost quazi-planar design and it is built using commercially available off the shelf parts.     

Bottom-series coupled quadrature VCO using the inductive gate voltage boosting technique

This article presents a new low-voltage bottom-series coupled quadrature voltage-controlled oscillator (QVCO), which consists of two n-core cross-coupled VCOs with the bottom-series coupling transistors. The low-voltage operation is obtained via an inductive gate voltage boosting technique. The proposed CMOS QVCO has been implemented with the TSMC 0.18?µm CMOS technology and the die area is 0.897?×?0.767?mm². At the supply voltage of 0.7?V, the total power consumption is 1.5?mW. The free-running frequency of the QVCO is tuneable from 3.77 to 4.12?GHz as the tuning voltage is varied from 0.0 to 0.7?V. The measured phase noise at 1?MHz frequency offset is ?123.35?dBc/Hz at the oscillation frequency of 4.12?GHz and the figure of merit of the proposed QVCO is ?193.5?dBc/Hz.     

Novel 53/106 GHz Dual-Band MMW LC Oscillator Implemented in SiGe BiCMOS Technology

In this Paper, we present a fully integrated millimeter wave LC voltage-controlled oscillator (VCO), which employs a novel topology, operating at dual-band frequency of 53.22 GHz-band and 106.44 GHz-band. The low-phase noise performance of ?107.3 dBc/Hz and ?106.1 dBc/Hz at the offset frequency of 600 kHz, ?111.8 dBc/Hz and ?110.6 dBc/Hz at the offset frequency of 1 MHz around 53.22 GHz and 106.44 GHz are achieved using IBM BiCMOS-6HP technology, respectively. Two tuning ranges, of 52.7 - 53.8 GHz and 105.4 - 107.6 GHz for the proposed LC VCO are obtained. The output voltage swing of this VCO is around 1.8 V_p-p at the operation frequency of 53.22 GHz and 0.45 V_p-p at 106.44 GHz; the total power consumption is about 16.5 mW. To our knowledge, this is the first oscillator which operates at dual-band frequency above 50 GHz with the best preformance.     

Comparison between RTW VCO and LC QVCO 12?GHz PLLs

This paper reports comparisons between RTW VCO and LC QVCO 12?GHz PLLs, designed in a 130?nm CMOS technology for satellite communication applications. The phase noise at 1?MHz offset from the carrier is ?102?dBc/Hz for the RTW VCO PLL and ?98?dBc/Hz for the LC QVCO PLL, and the power consumption is 39 and 17?mW, respectively.     

A 4.6 GHz cascade switched biasing LC–QVCO using source-body resistor

This paper presents a 4.6 GHz LC quadrature voltage-controlled oscillator (QVCO) in which the phase noise performance is improved by two methods: cascade switched biasing (CSB) technique and source-body resistor. The CSB topology can reduce the resonator loss caused by MOSFET resistance. Meanwhile, it can maintain the benefits of conventional switched biasing technique. The source-body resistors are utilized to reduce the noise contribution of the substrate related to the cross coupled MOSFETs. The proposed QVCO has been implemented in standard 0.18 μm CMOS technology. With the two methods mentioned above, it consumes 4.9 mW under 1 V voltage supply and achieves a phase noise of ?120.3 dBc/Hz at 1 MHz frequency offset from the carrier of 4.56 GHz. The figure of merit is 186.5 dBc/Hz and the tuning range is from 4.2 G to 5 GHz (17.3 %). When the QVCO operates at 0.8 V voltage supply, the power consumption is 2.88 mW and the phase noise is ?115.7 dBc/Hz at 1 MHz frequency offset from the carrier of 4.58 GHz.     

A local oscillator for WCDMA band VII based on frequency multiplication

This work explores the generation of a local oscillator for WCDMA band VII based on frequency multiplication of a GSM reference. The frequency multiplier is based on a PLL, which includes a compact VCO based on a ring oscillator. A proper PLL design allows to sufficiently reject the relative high VCO phase noise, complying with the WCDMA requirements. The effectiveness of the proposed approach is proved with the design of the whole multiplier in a 90?nm CMOS technology. The generated oscillation ranges from 3 to 6?GHz, while the simulated phase noise is ?120 and ?144?dBc/Hz at a frequency offset of 0.6?and 20?MHz, respectively, dissipating 6.3?mW.     

A Co‐design Study of Filters and Oscillator for Low Phase Noise and High Harmonic Rejection

In this paper, we present a novel oscillator (OSC) design. Bandpass filters, which can suppress harmonics, are incorporated into a co‐design with an OSC to improve the OSC phase noise and harmonic rejection. The proposed OSC/bandpass filter co‐design achieves a phase noise of ?130.1 dBc/Hz/600 kHz and harmonic rejection of 37.94 dB and 40.85 dB for the second and third harmonics, respectively, as compared to results achieved by the OSC before co‐design of ?101.6 dBc/Hz/600 kHz and 21.28 dB and 19.68 dB. Good agreement between the measured and simulated results is achieved.     

Conditions for optimum noise performance in l.f. amplifiers employing junction f.e.t.s

Increasing the drain current of an f.e.t. can result in an improvement of the noise performance at medium frequencies, but, owing to changes in the noise spectrum of the device, a deterioration of the low-frequency noise performance can result. Measurements in the frequency range 1 Hz?1 kHz on some low-noise samples of f.e.t.s show that the drain current is not critical up to a limit, but, above this limit, the noise performance below 10 Hz deteriorates rapidly.     

Fully integrated low phase noise multi-band LC-tank voltage controlled oscillator with switched-capacitor resonator

This paper presents the design and implementation of a fully integrated low noise multi-band LC-tank voltage-controlled-oscillator(VCO).Multi-band operation is achieved by using switched-capacitor resonator.Additional three-bit binary weighted capacitor array is also used to extend frequency tuning range in each band.To lower phase noise,two noise filters are added and a linear varactor is adopted.Implemented in a 0.18 μm complementary-metal-oxide-semiconductor(CMOS) process,the VCO achieves a frequency tuning range covering 2.26～2.48 GHz,2.48～2.78 GHz,2.94～3.38 GHz,and 3.45～4.23 GHz while occupies a chip area of 0.52 mm2.With a 1.8 V power supply,it draws a current of 10.9 mA,10.6 mA,8.8 mA,and 6.2 mA from the lowest band to the highest band respectively.The measured phase noise is-109～-120 dBc/Hz and-121～-131 dBc/Hz at a 1 MHz and 2.5 MHz offset from the carrier,respectively.     

A W-band Frequency Source with Low Spurs and Low Phase Noise

A W-band millimeter wave frequency source is developed by frequency multiplier chain and injection locking. The referenced crystal oscillator (CO) signal 120 MHz is multiplied 400 times to output 48 GHz signal. Then, it is used as a referenced source of fundamental-wave injection-locked harmonic Gunn oscillator with output power more than 10 mW at 96 GHz and spurious output less than ?65 dBc. The measured phase noise is ?97 and ?105 dBc/Hz at 10 kHz and 200 kHz offset, respectively. At last, the influence of the flicker noise, provided by the frequency multipliers and amplifiers, is analyzed.     

Symmetrical Mott barrier as a fast photodetector

A novel surface-oriented GaAs punch-through photodetector possessing a fast photoresponse and a moderate internal gain is described. The device has a simple planar MnM structure consisting of two Schottky contacts which thereby facilitate the fabrication. The detector exhibits an internal rise time as fast as 20 ps with a full width at half maximum (FWHM) of 35 ps. The internal gain of the detector was estimated to be 3. The noise equivalent power was measured to be 4×10?11 W/?Hz. The detector represents one of the fastest GaAs photodetectors reported to date.     

A low noise interface circuit design of micro-machined gyroscope

The analyses of MEMS gyroscope interface circuit on thermal noise, 1/f noise and phase noise are made in this paper. A closed-loop differential driving circuit and a low-noise differential detecting circuit based on the high frequency modulation are designed to limit the noise. The interface chip is implemented in a standard 0.5 μ m CMOS process. The test results show that the resolution of sensitive capacity can reach to 6.47 × 10^-20 F at the bandwidth of 60 Hz. The measuring range is ± 200°/s and the nonlinearity is 310 ppm. The output noise density is 5.8°/(h·√Hz). The angular random walk (allen-variance) is 0.092°/√h and the bias instability is 2.63°/h.     

Current-mode phase-locked loop with constant-Q active inductor CCO and active transformer loop filter

This paper presents a current-mode phase-locked loop (PLL) with a constant-Q CMOS active inductor current-controlled oscillator (CCO) and a CMOS current-mode active-transformer loop filter. The constant-Q active inductor provides a large and swing-independent quality factor such that the phase noise of the CCO utilizing the constant-Q active inductor is comparable to that of CCO with spiral inductors. The current-mode active-transformer loop filter offers the advantage of a large and tunable inductance and low silicon consumption such that the loop bandwidth of the PLL can be made small and tunable. The PLL was designed in TSMC-0.18 μm 6-metal 1.8V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3v3 device models. The phase noise of the PLL was analyzed using Cadence’s Verilog-AMS behavioral modeling. The phase noise of the CCO with the constant-Q active inductor is ?123.1 dBc/Hz at 1 MHz frequency offset, over 10 dB better as compared with that of the CCO with conventional active inductors, and is only a few dB higher than that of the CCO with spiral inductors. The phase noise of the PLL with an active-transformer loop filter and a constant-Q CCO is ?116 dBc/Hz at 1 MHz frequency offset, nearly 20 dB lower than that of the PLL with the same active-transformer loop filter and a conventional active-inductor CCO. The lock time, power consumption, and phase noise of the PLL are 60 ns, 34 mW, and ?116 dBc/Hz at 1 MHz frequency offset, respectively. The total silicon consumption of the PLL excluding bond pads is 0.013 mm².