Physics-of-failure assessment methodology for power electronic systems

Driven by consumer markets and industrial needs, power electronic systems are operating at higher power densities, in smaller packages and in more exotic environments. As these trends continue, ensuring long-term operation in harsher conditions requires accurate reliability prediction models, most viably obtained through Physics-of-Failure (PoF) methodologies. This paper introduces a PoF-based system-level reliability assessment procedure in which the dominant failure mechanisms are identified for three primary subsystems: the power module, DC-link capacitors and the control circuitry. This report outlines the dominant failure modes and mechanisms for each subsystem and provides examples of how to improve subsystem reliability based upon the described assessment methodology. A case study is also presented in which the solder interconnect reliability of the gate-driver board in a mid-range variable frequency drive (VFD) was assessed.     

Hybrid reliability assessment for packaging prototyping

The paper presents a physics-based hybrid approach to assist the assessment of thermally induced packaging reliability. This method is applicable to prototypes at different stages of development. The approach realizes the efficiency and effectiveness through some special capabilities in identifying reliability critical locations and evaluating deformation and failure mechanisms. These capabilities are facilitated by the computer vision techniques for multi-scale measurement, including, the digital speckle correlation and the phase-shifted shadow moiré. The techniques combine to become three-dimensional and capable of locating failure prone sites and obtaining failure related parameters at desired spatial resolution. The novelty comes as the experimental measurement is integrated with numerical and analytical modeling. An apparent merit is that the approach can bypass some uncertain issues that could cause deficiency of an assessment if a pure modeling or testing is employed. Following an introduction to the experimental techniques and procedures, application examples are presented to demonstrate the feasibility and the potential of the approach.     

Tutorial: temperature as an input to microelectronics-reliabilitymodels

This tutorial discusses various modeling methodologies for temperature acceleration of microelectronic-device failures; there are situations in which some methodologies give-misleading results. The aim is to raise the level of understanding of the impact of temperature on reliability and to define the objectives of physics-based temperature modeling. There are alternatives to both the Arrhenius relation and the MilHdbk-217 approach to reliability. In Japan, Taiwan, Singapore, and Malaysia, a physics-of-failure approach is used by most companies. Philips in the Netherlands and the CADMP Alliance in the USA have developed methods and software to conduct physics-based reliability assessments     

Reliability Object Model Tree (ROM-Tree): A system design-for-reliability method

Designing complex systems that satisfy reliability requirements is a challenge because of complex assembly structures and logical connections, numerous components and associated failure modes, limited reliability data or prediction models, and multi-disciplinary considerations. To overcome these difficulties and to design reliable systems in a systematic way, we have developed a system design-for-reliability (SDfR) method, called Reliability Object Model Tree (ROM-Tree). The developed ROM-Tree consists of: (1) a new reliability analysis structure, (2) reliability metrics, and (3) reliability activities. ROM-Tree is demonstrated through a case study in electronic system designs. Results show that the ROM-Tree method is useful in supporting SDfR in a unified way.     

Integration of analytical techniques in stochastic optimization of microsystem reliability

This paper presents an integrative application of several numerical analytical techniques and associated analysis tools for design optimization and damage prediction in electronics packages and microsystems. This design-for-reliability approach is based on four different types of numerical techniques that allow (1) high-fidelity modelling, (2) reduced order modelling, (3) numerical optimization and (4) uncertainty analysis. The capabilities and the characteristics of the methods that underpin these four types of modelling and analysis tools are firstly investigated. The integration of the methods and tools is then examined and a methodology for coupling the tools in an optimization process is proposed. This numerical methodology involves the following steps: (1) Define sampling points for the design of interest by design of experiments (DOE) and calculate the design response at each DOE point using high-fidelity analysis; (2) construct reduced order models (ROM) for fast analysis using the obtained response values at the DOE points; (3) Undertake deterministic optimization in the defined design space by ROM; and (4) Probabilistic optimization by including variation and uncertainty of the design in the optimization task. This approach is suitable to address design-for-reliability requirements at early design stages in a wide range of application areas. The application of this approach is demonstrated in a case for minimizing the thermal fatigue damage of flip-chip solder interconnects. Design modifications show that this approach can provide improved reliability of the package and in the same time satisfy a number of design requirements.     

Life tests of SSI integrated circuits

Some results as well as a new and simple method of digital IC life testing are dealt with here referring to the beginning of a large-scale test programme which started 2 yr ago. As the first step, bipolar SSI digital IC-s of the TTL, DTL and RTL series have been considered comprising about 60 million device-hr, life-tested by various long-run stress methods as temperature storage, d.c.-and switching-service operational tests to gain a fair picture on main failure mechanisms, the nature and shift tendencies of parameter distributions as well as on the activation energy of degradation processes—besides the estimation of characteristic failure rates in various stress forms—to facilitate the use of accelerated methods and to rendering possible the optimal choice among testing methods for future reliability assessment work. It has been shown that temperature activation energies of approx. 1·0 eV—essentially the same as at discrete planar transistors—are resulted if “side” effects of experiments are carefully avoided.     

Comparison of reliability impacts of two active power curtailment methods for PV micro-inverters

The future generation of solar PV inverters will have to be equipped with new grid supporting functionalities. One of them is the active power curtailment (APC) for overvoltage prevention. New functionalities can be challenging from the design-for-reliability aspect. This is especially true for micro-inverters, due to their outdoor application and more extreme environmental conditions. In this paper, two APC designs are considered and their impact on component reliability is predicted using 217Plus™ empirical method. The analyzed components are DC bus capacitors, DC–DC MOSFETs and an AC protection relay. The study reveals that APC can decrease the failure rate of MOSFETs and capacitors. Depending on the selected APC method the capacitor failure rate reduction is either 6% or 54%, but the latter benefit comes with a trade-off for a high failure rate increase of the AC relay. The failure rates are not significant from warranty perspective, but indicative enough for making preliminary design-for-reliability recommendations.     

Electrical characterization and modification of a microelectroMechanical system (MEMS) for extended mechanical reliability and fatigue testing

The feasibility of microsystems has been achieved in the early 90's and is now followed by a growing industrialization period. Nevertheless, diversity of fields combined and materials heterogeneity generate new failure mechanisms different from traditional microelectronics. Now, if we take into account the lessons from the past in microelectronics, we note that failure analysis played a major role not only in development time reduction but also in qualification and reliability evaluation. That is why we decided to elaborate a specific failure analysis methodology for microsystems using existing instrumentation from microelectronics in order to prepare for present and future expert appraisement requirements in the micro-technologies field.For this, we chose to perform accelerated aging tests of a commercial micro-accelerometer. This paper demonstrates how we realized the reverse engineering of this MicroElectroMechanical System (MEMS) using an Electron Beam Tester (Integrated Diagnostic System : IDS-5000) and how we modified its functions with a Focused Ion Beam (FIB-P2X) in order to control its full mechanical capabilities with electrical stimulation.     

Physics-based simulation techniques for small- and large-signal device noise analysis in RF applications

The paper presents a review on physics-based noise simulation techniques for RF semiconductor devices, starting with the small-signal case but with greater stress on noise in large-signal (quasi)-periodic operation. The nonautonomous (forced) operation case will be considered, which is relevant to all RF applications apart from oscillators. Besides their importance in device design, physics-based noise models can also suggest viable and correct strategies to implement circuit-oriented models, e.g., compact models. From this standpoint, the connection between physics-based and circuit-oriented modeling is discussed both in the small-signal and in the large-signal case, with particular stress on the treatment of colored noise in the large-signal periodic regime.     

Charge transport in high-κ stacks for charge-trapping memory applications: A modeling perspective (invited)

Charge trapping (CT) memories could be a promising technology option for further NAND Flash scaling. The assessment of the scalability limits and ultimate performances of this technology demands for the comprehensive understanding of the physical mechanisms governing device operation and reliability, which requires accurate physics-based models reproducing the electrical device characteristics. The basic features of the models presented in the literature for CT memory devices are reviewed, underlining their similarities and differences, and highlighting their importance in order to achieve a comprehensive understanding of the physical mechanisms responsible for CT device operation and reliability. A physical model describing the charge transport in nitride and high-κ stacks is also presented, which allows gaining further insights into reliability issues related to charge localization and high-κ tunnel and blocking dielectrics, like the effects of the blocking alumina layer and the band-gap engineered tunnel dielectrics on the TANOS device retention.     

Advanced experimental and computational tools for robust evaluation of on-chip interconnect reliability

Two technologies are introduced that, together, provide a platform for robust evaluation of interconnect reliability. One is the DISMAP technology, which provides plots of the displacement and strain fields of cross-sectioned interconnect structures under various loading conditions. Measurements provided by DISMAP reveal how multilevel-interconnect structures interact structurally, for example what type of strain fields exist during thermal cycling. A complimentary technology, known as probabilistic analysis, is also described and applied using the NESSUS software. Probabilistic analysis combines statistical uncertainty with physics-based models to predict the probability of failure and also to reveal the relative importance of the various uncertainties associated with interconnect manufacturing. By comparing the predictions of physical models to DISMAP measurements, the validity of those models are evaluated.     

Wireless smart implants dedicated to multichannel monitoring and microstimulation

Innovative circuits and systems techniques are required to build advanced smart medical devices (SMD). The high reliability and very low power consumption are among the main criteria that must be given priority to implement in such implantable and wirelessly controlled microsystems. A typical device is composed of several integrated modules to be assembled on a thin substrate providing placement flexibility in the body. Monitoring of electrode-tissue interface condition is needed for enhanced safety, and for enabling troubleshooting after implantation. In order to improve controllability and observability, fully integrated binary phase-shift-keying (BPSK) demodulation combined with a passive modulation method allows full-duplex data high data rate communication between external controllers and implants. Case studies such as peripheral nerve interfaces to recuperate bladder functions, cortical multichannel stimulator, as well as cortical monitoring devices are reported.     

An architecture for self-test of a wireless communication systemusing sampled IQ modulation and boundary scan

An architecture for system-level self-test of a wireless communication transceiver integrates the functional (parametric) self-test of the radio frequency subsystem, and the structural self-test of the digital subsystem. The digital subsystem is tested using extensions of the IEEE 1149.1 boundary scan standard to verify connections within circuit boards and between boards. The RF subsystem is tested using a loopback connection between the RF transmitter and receiver. An RF parametric self-test is performed using a digitally modulated signal (as opposed to a sinusoidal tone) as the test stimulus, and using samples from the receiver digitizer as test data. This loopback test scheme imposes a relatively small overhead on the RF system design     

Capacitive RF MEMS analytical predictive reliability and lifetime characterization

The reliability of integrated systems is considered as a major obstacle in their development. The goal of this work is to estimate the lifetime of RF MEMS capacitive switch devices. This is performed by combining the functional and physical failure analysis models using the VHDL-AMS language. The physics of charging effects along with mechanical behavior of the membrane are introduced simultaneously to determine the time to failure.     

射频微系统冷却技术综述

雷达、电子战等射频电子装备向高集成度和大功率方向发展,有力牵引了射频微系统技术的进步,同时给冷却设计带来三大挑战:高面热流度、热堆叠和高体热流密度。冷却技术成为制约射频微系统应用的关键瓶颈之一。文中综述了国内外当前射频微系统冷却技术的发展现状,传统的远程散热架构因界面多与传热路径远已难以为继,高集成度的近结冷却技术显著提升芯片散热能力;以有源相控阵雷达为例,提出了射频微系统冷却的三代技术路线,指出了射频微系统热设计的主要发展方向。     

An improved reliability model for Si and GaN power FET

The existing standard reliability models for power devices are not satisfactory and they fall short of predicting failure rates or wear-out lifetime of semiconductor products. This is mainly attributed to two reasons; the lack of a unified approach for predicting device failure rates and the fact that all commercial reliability evaluation methods relay on the acceleration of one dominant failure mechanism. Recently, device reliability research programs are aimed to develop new theoretical models and experimental methods that would result a better assessment of the device lifetime as well as point out on the dominating failure mechanism for particular operating conditions. A new model, named Multi failure mechanism, Overstress Life test (MOL) has been introduced and posed a better understanding of the dominating failure mechanisms under various stressed conditions in advanced FPGA devices (for 45 and 28 nm technologies). In this work we present, for the first time, the implementation of the MOL model to investigate the reliability of silicon power MOSFET and GaN power FET devices. Both, LTSpice simulation and experimental data are presented for a test circuit of a ring oscillator, based on CMOS-FET, NMOS-FET, PMOS-FET and N-channel e-GaN FET. The monitored data was acquired in-situ in form of the ring frequency or Vds values that enabled to assess the lifetime and determine the dominating mechanism during accelerated wearout by temperature, applied bias voltage, thermal cycling, gamma and electron irradiation. Moreover, in the case of GaN devices, RDS-On monitoring circuit has also been operated during thermal cycling of the tested component and the acceleration factor was derived for various operational parameters.     

Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect andadd/drop multiplexer solution

This paper presents a single-chip all-CMOS solution for 4×OC-3c, OC-12, and OC-12c synchronous digital hierarchy/synchronous optical network (SDH/SONET) framing with integrated serial line interfaces. Outstanding features of this chip are clock and data recovery and fulfillment of ITU-T and Bellcore jitter requirements for SDH/SONET systems, as well as the large range of functions offered. These functions include asynchronous transfer mode (ATM) and point-to-point protocol (PPP) support, as well as built-in native SDH/SONET functions such as digital cross-connect, add/drop multiplexing, and automatic protection switching. In addition, the chip is based on a new scalable modular architecture     

SMA电缆组件失效分析及改进

SMA射频同轴连接器插头构成的SMA电缆组件广泛地应用于各种产品及测试系统中。主要通过对SMA电缆组件失效模式及机理的分析,提出相应的改进措施,希望能够达到提高电缆组件可靠性的目的,并推广应用到类似结构的电缆组件。     

Demonstration of photonically controlled GaAs digital/MMIC for RFoptical links

We report design, fabrication, and test of a monolithic GaAs optoelectronic integrated circuit (OEIC) implementing a broad-band optically driven digital/analog radio frequency (RF) interface. The integrated circuit (IC) was fabricated using a foundry-compatible enhancement/depletion metal-semiconductor field-effect transistor (MESFET) process with no added lithography steps. A single optical fiber carries externally amplitude modulated 0.85-μm light to the on-chip GaAs metal-semiconductor-metal interdigitated photodetector. RF as well as simultaneous digital information encoded at up to 10 Mb/s using a novel waveform set is transmitted over the fiber. The serial digital data is self-clocked into on-chip registers to control the RF signal chain, which includes a three-bit digital attenuator. The circuit operates in an asynchronous mode to detect digital and RF on the single optical-fiber input, control RF level, and transmit the 2-8-GHz RF to the IC's electrical output. Measurements characterizing the RF and digital performance of the IC as well as a demonstration of the full optoelectronic mixed-mode functioning of the IC are presented