Enhancement of test data compression with multistage encoding

In this paper, we present two multistage compression techniques to reduce the test data volume in scan test applications. We have proposed two encoding schemes namely alternating frequency-directed equal-run-length (AFDER) coding and run-length based Huffman coding (RLHC). These encoding schemes together with the nine-coded compression technique enhance the test data compression ratio. In the first stage, the pre-generated test cubes with unspecified bits are encoded using the nine-coded compression scheme. Later, the proposed encoding schemes exploit the properties of compressed data to enhance the test data compression. This multistage compression is effective especially when the percentage of do not cares in a test set is very high. We also present the simple decoder architecture to decode the original data. The experimental results obtained from ISCAS'89 benchmark circuits confirm the average compression ratio of 74.2% and 77.5% with the proposed 9C-AFDER and 9C-RLHC schemes respectively.     

一种减少BIST测试资源的高级寄存器分配算法

在高级综合阶段考虑电路的可测性有许多优点，包括降低硬件开销，减少性能的下降，并达到更高的测试效率等。本文提出了一种基于伪随机可测性方法的寄存器分配算法，来减少内建自测试（BIST）所带来的硬件开销。在基准电路上的实验结果表明：与其它BIST测试综合方法相比较，采用本论文所提的方法进行测试综合对测试资源占用最多可以降低46.8%.     

Capture-power-aware test data compression using selective encoding

Ever-increasing test data volume and excessive test power are two of the main concerns of VLSI testing. The “don’t-care” bits (also known as X-bits) in given test cube can be exploited for test data compression and/or test power reduction, and these techniques may contradict to each other because the very same X-bits are likely to be used for different optimization objectives. This paper proposes a capture-power-aware test compression scheme that is able to keep capture-power under a safe limit with low test compression ratio loss. Experimental results on benchmark circuits validate the effectiveness of the proposed solution.     

Hardware compression scheme based on low complexity arithmetic encoding for low power image transmission over WSNs

Software implementation costs of most algorithms, designed for image compression in wireless sensor networks, do not justify their use to reduce the energy consumption and delay transmission of images. Even though the hardware solution looks to be very attractive for this problem, a specific care should be paid when designing a low power algorithm for image compression and transmission over these systems. The aim of this paper is to present and evaluate a hardware implementation for user-driven image compression scheme designed to respect the energy constraints of image transmission over wireless sensor networks (WSNs). The proposed encoder will be considered as a co-processor for tasks related with image compression and data packetization. In this paper, we discuss both of the hardware architecture and the features of this encoder circuit when prototyped on FPGA (field-programmable gate array) and ASIC (application-specific integrated circuit) circuits.     

A test set embedding approach based on twisted-ring counter with few seeds

Test data storage, test application time and test power dissipation increase dramatically for single stuck-at faults while tens of million gates are integrated in a System-on-a-Chip (SoC), which makes implementing fault testing for embedded cores based SoC become a challenging task. To further reduce test data storage, test application time and test power dissipation, this paper presents a new test set embedding approach based on twisted-ring counter (TRC) with few seeds. This approach includes two improvements. The first is that an efficient seed-selection algorithm is employed to exploit the high-density unspecified bits in the deterministic test set and so the test data storage for complete coverage of single stuck-at faults is minimized. The second is that a novel test-sequence-reduction scheme based on shifting seeds is proposed to reduce test application time that in turn reduces test power dissipation. Compared with the conventional approach, experiments on ISCAS’89 benchmark circuits show that the proposed approach requires 65% less test data storage, 68% shorter test application time and 67% less test power dissipation. Moreover, its hardware overhead is very small.     

An innovative two-stage data compression scheme using adaptive block merging technique

Test data has increased enormously owing to the rising on-chip complexity of integrated circuits. It further increases the test data transportation time and tester memory. The non-correlated test bits increase the issue of the test power. This paper presents a two-stage block merging based test data minimization scheme which reduces the test bits, test time and test power. A test data is partitioned into blocks of fixed sizes which are compressed using two-stage encoding technique. In stage one, successive blocks are merged to retain a representative block. In stage two, the retained pattern block is further encoding based on the existence of ten different subcases between the sub-block formed by splitting the retained pattern block into two halves. Non-compatible blocks are also split into two sub-blocks and tried for encoded using lesser bits. Decompression architecture to retrieve the original test data is presented. Simulation results obtained corresponding to different ISCAS′89 benchmarks circuits reflect its effectiveness in achieving better compression.     

ATM网络中语音编码和传输的新方案

本文针对未来新的ＡＴＭ通信方式,提出了一种新的语音可变速率编码和可变时延传输系统方案,为了将信号源和人耳听觉的特征,与ＡＴＭ网络的统计复用性相结合,实现语音的码率在缩和低时延传输,该方案将ＡＴＭ网络环境和语音编码系统中最优信号分析区间的选取、编码系统参数的确定相结合。文中基于一种新的分布熵进行信号特征判断,对输入信号构成不同的处理系统,具体编码由小波变换分带、多带二进树ＶＱ构成,输出码率可调,改变     

Core-unified soc test data compression and application

The pattern run-length coding test data compression approach is extended by introducing don’t care bit (x) propagation strategy into it. More than one core test sets for testing core-based System-on-Chip (SoC) are unified into a single one, which is compressed by the extended coding technique. A reconfigurable scan test application mechanism is presented, in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added. The proposed union test technique is applied to an academic SoC embedded by six large ISCAS’89 benchmarks, and to an ITC’ 02 benchmark circuit. Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores, the proposed scheme can not only improve test data compression/decompression, but also reduce the redundant shift and capture cycles during scan testing, de-creasing SoC test application time effectively.     

Test data compression using alternating variable run-length code

This paper presents a unified test data compression approach, which simultaneously reduces test data volume, scan power consumption and test application time for a system-on-a-chip (SoC). The proposed approach is based on the use of alternating variable run-length (AVR) codes for test data compression. A formal analysis of scan power consumption and test application time is presented. The analysis showed that a careful mapping of the don’t-cares in pre-computed test sets to 1s and 0s led to significant savings in peak and average power consumption, without requiring slower scan clocks. The proposed technique also reduced testing time compared to a conventional scan-based scheme. The alternating variable run-length codes can efficiently compress the data streams that are composed of both runs 0s and 1s. The decompression architecture was also presented in this paper. Experimental results for ISCAS'89 benchmark circuits and a production circuit showed that the proposed approach greatly reduced test data volume and scan power consumption for all cases.     

METHOD OF VECTOR QUANTIZATION CODING USING RECTANGULAR TRANSFORM FOR IMAGE COMPRESSION

First of all a simple and practical rectangular transform is given,and then thevector quantization technique which is rapidly developing recently is introduced.We combinethe rectangular transform with vector quantization technique for image data compression.Thecombination cuts down the dimensions of vector coding.The size of the codebook can reasonablybe reduced.This method can reduce the computation complexity and pick up the vector codingprocess.Experiments using image processing system show that this method is very effective inthe field of image data compression.     

基于能量树编码的小波图像压缩算法

针对小波变换的空间能量聚集特性,提出了一种基于能量树编码的小波图像压缩算法。该算法在离散小波变换的基础上,分别对图像的各高频子带按其局部能量构建分层能量树,利用总能量和各层的能量角等效表示子带的小波系数;根据给定的压缩比,选择合适的代价函数构建最佳能量树,然后对其进行量化和编码,通过自适应的比特率分配实现小波图像压缩。实验结果表明,该算法实现简单,重构图像质量好,与当前多种主流的小波图像压缩算法相比,压缩性能有了明显提高。     

基于FDR码改进分组的SoC测试数据压缩方法

文章提出一种基于FDR码改进分组的SoC测试数据压缩方法.经过对原始测试集无关位的简单预处理,提高确定位0在游程中的出现频率.在FDR码的基础上,改进其分组方式,通过理论证明其压缩率略高于FDR编码,尤其是短游程的压缩率.用C语言编写程序模拟两种编码方法的软件实现程序,实验结果证明了改进分组的FDR编码方法的有效性和高压缩性.     

一种数据包合并跨层优化编码方案

在传统分层系统中,信息数据包首先在数据链路层进行数据包级的检错码编码,然后一个数据包对应一个信息分组在物理层进行符号级的纠错码编码,最后送入信道中传输。为提高系统的传输效率,提出了一种基于数据包合并的物理层与数据链路层编码的跨层优化方案,即数据链路层的多个数据包合并对应物理层的一个信息分组,然后进行纠错编码后再传输。通过理论推导得出了使系统传输效率最大的最优合并数据包个数和数据包长度表达式。通过仿真验证了理论推导的正确性,并与传统方案进行了比较,结果表明,该方案能有效提高系统的传输效率。     

基于零树的视频压缩加密联合编码方案

针对可伸缩性视频流的安全性问题，提出了一种与编码相结合的加密方案。该方案以小波变换作为压缩平台，通过在零树生成的过程中对零树符号进行加密来保证视频的安全性，并且采用分级加密来满足不同用户对不同质量服务的需求。实验证明该方案一方面保持了编码的可伸缩性，另一方面提高了视频流的安全性，并且加密处理对压缩效率影响小，适用于网络上的视频流服务。     

基于TMS320DM8168的视频编码系统研究与实现

随着信息技术的进步,空间对地成像已朝着高清、多路方向发展。基于通用DSP和H.264/AVC视频编码标准的实时视频压缩系统,由于具有开发周期短、可靠性高、处理速度快、便于升级以及体积小、功耗低、适应性强等优点,可以为新的需求提供解决方案,研究基于通用DSP、采用先进视频压缩技术的实时视频编码器具有重要意义。为满足越来越多的高清视频采集、编码和传输的应用需求,基于TI的新一代多核DSP TMS320DM8168芯片,给出了方案的设计与实现,在该系统上实现了H.264视频编码算法,可对输入的双路1080p视频进行60 fps实时编码压缩。方案的主处理器只需一片DSP,与传统多路视频压缩方案需要多片处理器相比,这种高度集成方案降低了部件数量和物料(BOM)成本、功耗需求,缩小了PCB尺寸,提高系统集成度。     

A Built-In Self-Test structure for measuring gain and 1-dB compression point of Power Amplifier

This paper proposes a Built-In Self-Test (BIST) structure for measuring the gain and the 1-dB compression point of the Power Amplifier (PA) in transceiver ICs. In this structure, it is not necessary to use the external devices for mapping and DC measuring because of linearity of blocks, comparative performance in the linear region and the digital representation of the 1-dB compression point and gain value. The BIST Circuit is designed and simulated in 180 nm RF-CMOS process with Spectre-RF for a 900 MHz PA while it can achieve an acceptable accuracy which the input referred 1-dB compression point and gain value can be obtained with an error of about 0.2 dBm and 0.18 dB, respectively and the testing time is about 25 µs depends on resolution. Finally, in order to verify the proposed approach, we implemented practically a similar discrete circuit as proof-of-concept prototype that it obtained input referred 1-dB compression point value with an error of about 0.15 dBm.     

Split variable-length input Huffman code with application to test data compression for embedded cores in SOCs

In this article, a run length encoding-based test data compression technique has been addressed. The scheme performs Huffman coding on different parts of the test data file separately. It has been observed that up to a 6% improvement in compression ratio and a 29% improvement in test application time can be achieved sacrificing only about 6.5% of the decoder area. We have compared our results with the other contemporary works reported in the literature. It has been observed that for most of the cases, our scheme produces a better compression ratio and that the area requirements are much less.     

Sensor data compression based on MapReduce简

A compression algorithm is proposed in this paper for reducing the size of sensor data. By using a dictionary-based lossless compression algorithm, sensor data can be compressed efficiently and interpreted without decompressing. The correlation between redundancy of sensor data and compression ratio is explored. Further, a parallel compression algorithm based on MapReduce [1] is proposed. Meanwhile, data partitioner which plays an important role in performance of MapReduce application is discussed along with performance evaluation criteria proposed in this paper. Experiments demonstrate that random sampler is suitable for highly redundant sensor data and the proposed compression algorithms can compress those highly redundant sensor data efficiently.     

关于一种算术编码数据加密方案的密码分析

本文分析了一种基于算术编码的数据加密方案。如果采用原方案的加密算法,则密文表达式有误,解密算法不能得出正确的明文,且破译者能在O(n^2)内求出密钥,如果采用原方案的解密算,破译者也可在O（n^2)内求出密钥,从而彻底的攻破了这种体制。     

Low-complexity compression of multispectral images based on classified transform coding

Compression of remote-sensing images can be necessary in various stages of the image life, and especially on-board a satellite before transmission to the ground station. Although on-board CPU power is quite limited, it is now possible to implement sophisticated real-time compression techniques, provided that complexity constraints are taken into account at design time. In this paper we consider the class-based multispectral image coder originally proposed in [Gelli and Poggi, Compression of multispectral images by spectral classification and transform coding, IEEE Trans. Image Process. (April 1999) 476–489 [5]] and modify it to allow its use in real time with limited hardware resources. Experiments carried out on several multispectral images show that the resulting unsupervised coder has a fully acceptable complexity, and a rate–distortion performance which is superior to that of the original supervised coder, and comparable to that of the best coders known in the literature.