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1.
《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1981,69(10):1200-1211
The purpose of a digital synthesis aid is to allow a digital system architect to describe the behavior of a system to be built and to then aid him in the logic design of that system. This paper will overview several different approaches to the development of synthesis aids. The importance of key features of synthesis aids, such as the automatic generation of multilevel system representations, will also be discussed. 相似文献
2.
Advances in VLSI technology are making it feasible to pack millions of transistors on a single chip. A consequent increase in the number of on-chip faults as well as the growing importance of quality-metrics such as reliability and fault-tolerance are making on-chip fault-tolerance mandatory. On-chip realization of a computation is fault-secure if an observable error in the computation is detected. Components used in life-critical systems should be secured against all faults. While fault-security can be realized by duplicating the computation on disjoint hardware and voting on the result(s), such straightforward strategies entail appreciable hardware overhead. This paper presents computer-aided behavioral synthesis of fault-secure microarchitectures which require less than proportional increase in hardware. The strategy selects intermediate computations for additional voting. The resulting class of fault-secure microarchitectures supplants the enormous hardware requirements of naive fault-secure strategies with enhanced hardware utilization afforded by securing the intermediate computations. Experimental results show that fault-security can be implemented at a less than proportional increase in hardware overhead 相似文献
3.
Biesenack J. Koster M. Langmaier A. Ledeux S. Marz S. Payer M. Pilsl M. Rumler S. Soukup H. Wehn N. Duzy P. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1993,1(3):244-253
In this paper we present the Siemens high-level synthesis system CALLAS and describe its design methodology and synthesis strategy. It supports the synthesis of control-dominated applications and uses a VHDL subset for the algorithmic specification. Its main feature can be characterized as “What you simulate is what you synthesize.” This principle permits a validation of the synthesis results by simulation or even formal verification. CALLAS has been successfully applied on real designs which were implemented in silicon. These examples demonstrate that CALLAS fulfils the constraints and objectives of a hardware designer. The circuits are comparable in quality to results achieved by synthesis starting at the register-transfer-level 相似文献
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Duncan A.A. Hendry D.C. Gray P. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2001,9(1):218-223
This paper describes the column oriented butted regular architecture-algorithmic behavioral synthesis (COBRA-ABS) high-level synthesis tool which has been designed to synthesize DSP algorithms, specified in C, onto multi-field programmable gate array (FPGA) custom computing machines (FCCMs). COBRA-ABS performs synthesis using a new simulated annealing-based methodology, which maps the specified behavior into a four-dimensional (4-D) space and then optimizes the implied architecture. COBRA-ABS synthesizes custom very long instruction word (VLIW) style architectures partitioned across the FPGAs of the FCCM and has been used to compile C algorithms down to FPGA configuration bit-streams. This paper describes the tool and synthesis concepts and presents simulation results from a number of synthesized fast Fourier transform (FFT) related algorithms 相似文献
6.
In this article we propose two novel methods to improve the testability of the designs produced by high-level synthesis tools. Our first method, loop-breaking algorithm, identifies self-loops in a design generated by a high-level synthesis system and eliminates as many of these loops as possible by altering the register and module bindings. The second method, BINET with test cost, is a binding algorithm that takes the cost of testing into account during the binding phase of the high-level synthesis. The test cost considered in this article is a function of the number of self-loops in the synthesized design. Thus it generates only those solutions that have fewer if any self-loops. Finally we put the two methods together in which we first use BINET with test cost to produce nearly self-loop free designs and we further improve their testability by using the loop-breaking algorithm. We applied these methods to synthesis benchmark circuits and the results of our study, given in this article, show that the designs produced by our method have indeed reduced testability overhead and improved testability. 相似文献
7.
Nourani M. Papachristou C. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2000,8(4):431-435
This paper presents new algorithms for the scheduling and allocation phases in high-level synthesis under time and resource constraints. This is achieved by formulating these problems in terms of Liapunov's stability theorem using a transformation technique between the design space and the dynamic system space. These algorithms are based on moves in the design space, which correspond to the moves toward the equilibrium point in the dynamic system space. The scheduling algorithm (MFS) takes care of mutually exclusive operations, loop folding, multicycle operations, chained operations, and pipelining (structural and functional). The mixed scheduling-allocation algorithm (MFSA) can handle all of the above scheduling applications as well as simultaneously performing allocation of functional units, registers, and interconnects while minimizing the overall cost 相似文献
8.
Bergamaschi R.A. Kuehlmann A. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1993,1(3):233-243
High-level synthesis has been an active research field since the early eighties. However, apart from a few exceptions the technology has so far failed to make a smooth transition into the industrial environment. The main reasons are related more to the lack of an integrated methodology, including design entry, simulation, and synthesis, than to the quality of the synthesis algorithms. Experiences in applying the HIS system (High-level IBM Synthesis System) to real designs led to the development of a system and methodology which integrate language modeling, simulation, high-level, and logic synthesis. This paper presents the main concepts behind this system, namely, its modeling, synthesis, and simulation capabilities. Moreover, it addresses some of the problems encountered when transferring high-level synthesis to a production environment 相似文献
9.
Badaroglu M. Van der Plas G. Wambacq P. Donnay S. Gielen G.G.E. De Man H.J. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(1):23-33
Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore important to know the amount of noise at a certain point on the substrate. Existing transistor-level simulation approaches based on a substrate model extracted from layout information are not feasible for digital circuits of practical size. This paper presents a complete high-level methodology, which simulates a large digital standard cell-based design using a network of substrate macromodels, with one macromodel for each standard cell. Such macromodels can be constructed for both EPI-type and bulk-type substrates. Comparison of our substrate waveform analysis (SWAN) to several measurements and to several full SPICE simulations indicates that the substrate noise is simulated with our methodology within 10%-20% error in the time domain and within 2 dB relative error at the major resonance in the frequency domain. However, it is several orders of magnitude faster in CPU time than a full SPICE simulation. 相似文献
10.
In systems synthesis the basic lesson-and the hardest to accept-is that not all engineering problems can be or should be solved by deduction from mathematical and scientific principles. Synthesis is provisional and qualitative, a way of thinking different from the definitive, quantitative thinking of analysis. Its technique and tools reflect this difference. In synthesizing the system's initial concept, three qualitative techniques are fundamental: heuristics, metaphors, and models. Heuristics are brief statements of lessons learned in the past and applicable to the present situation. Metaphors transpose the implicit behavior of a system to a more familiar context, one example is the desktop metaphor for personal computer operating systems. Models are used to present different perspectives of a proposed system to multiple stakeholders so that everyone has a common frame of reference for discussion. Progressive modeling emphasizes the continuing refinement of models during system development than, say, an initial sketch to full-scale simulator. Each of these qualitative techniques are discussed. 相似文献
11.
《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1981,69(10):1321-1333
This paper is intended to be both a tutorial on hardware testing and a brief survey of existing techniques. Testing is discussed at all levels in the digital system hierarchy as well as at every stage of a system's life. The paper is organized into three parts. In the first part, fundamental concepts are presented. The second part reviews various testing techniques, with special emphasis on those that have gained wide acceptance. Finally, design techniques which promise to produce "easily testable" hardware are explored. 相似文献
12.
《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1978,66(10):1109-1125
Fault-tolerance is the architectural attribute of a digital system that keeps the logic machine doing its specified tasks when its host, the physical system, suffers various kinds of failures of its components. A more general concept of fault-tolerance also includes human mistakes committed during software and hardware implementation and during man/machine interaction among the causes of faults that are to be tolerated by the logic machine. This paper discusses the concept of faulttolerance, the reasons for its inclusion in digital system architecture, and the methods of its implementation. A chronological view of the evolution of fault-tolerant systems and an outline of some goals for its further development conclude the presentation. 相似文献
13.
A 0–1 integer linear programming (ILP) technique is used to solve memory-mapping problems in high-level synthesis, which synthesizes the source memory using one or more memory modules from a target memory library at a higher level. This method can not only perform bit-width mapping and word mapping, but it can also perform port mapping at the same time. Experimental results indicate that ILP approach is an effective method for memory reuse in high-level synthesis. 相似文献
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Emmanuel CasseauAuthor Vitae 《Integration, the VLSI Journal》2012,45(1):9-21
In a mobile society, more and more devices need to continuously adapt to changing environments. Such mode switches can be smoothly done in software using a general purpose processor or a digital signal processor. However hardware cores only can cope with both throughput and power consumption constraints. Reconfigurable hardware platforms provided by FPGA devices offer partial reconfiguration at runtime. However they require too long reconfiguration times and they cannot satisfy mobile device power consumption requirements. In this article we propose a methodology to map selected groups of DSP tasks to multi-mode cores using conventional hardware technologies. 相似文献
16.
数字通信系统中自适应均衡技术的研究 总被引:6,自引:0,他引:6
克服数字通信系统码间干扰的有效方法就是在接收端采用均衡技术。文中给出了均衡问题的数学描述,综述了实现均衡的方法,讨论了基于LMS和基于RLS的自适应均衡算法,并通过MATLAB仿真比较了两类算法的性能。 相似文献
17.
Hinton H.S. Cloonan T.J. McCormick F.B. Jr. Lentine A.L. Tooley F.A.P. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1994,82(11):1632-1649
Within the past 15 years there has been significant progress in the development of two-dimensional arrays of optical and optoelectronic devices. This progress has, in turn, led to the construction of several free-space digital optical system demonstrators. The first was an optical master-slave flip-flop using Hughes liquid-crystal light valves as optical logic gates and computer-generated holograms as the gate-to-gate interconnects. This was demonstrated at USC in 1984. Since then there have been numerous demonstrations of free-space digital optical systems including a simple optical computing system (1990) and five switching fabrics designated System1 (1988), System2 (1989), System3 (1990), System4 (1991) and System5 (1993). The main focus of this paper will be to describe the five switching fabric demonstrators constructed by AT&T in Naperville, IL. The paper will begin with an overview of the SEED technology which was the device platform used by the demonstrators. This will be followed by a discussion of the architecture, optics, and optomechanics developed for each of the five demonstrators 相似文献
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Spur-reduced digital sinusoid synthesis 总被引:1,自引:0,他引:1
This paper presents and analyzes a technique for reducing the spurious signal content in digital sinusoid synthesis. Spur reduction is accomplished through dithering amplitude and phase values prior to wordlength reduction. The analytical approach developed for analog quantization is used to produce new bounds on spur performance in these dithered systems. Amplitude dithering allows output wordlength reduction without introducing additional spurs. Effects of periodic dither similar to that produced by a pseudo-noise (PN) generator are analyzed. This phase dithering method provides a spur reduction of 6(M+1) dB per phase bit when the dither consists of M uniform variates. While the spur reduction is at the expense of an increase in system noise, the noise can be made white, making the noise power spectral density small. This technique permits the use of a smaller number of phase bits addressing sinusoid look-up tables, resulting in an exponential decrease in system complexity. Amplitude dithering allows the use of less complicated multipliers and narrower data paths in purely digital applications, as well as the use of coarse-resolution, highly-linear digital-to-analog converters (DAC's) to obtain spur performance limited by the DAC linearity rather than its resolution 相似文献
20.
The conflict between two published fault-tolerant digital clocking systems is resolved and a new design is given. 相似文献