一种小型化微波频率合成器

该频率合成器的特点是体积小(112×114×95)、重量轻(1kg)、监测装置齐备、工作稳定可靠、使用方便、造价低,在卫星通信中得到了广泛应用。     

带高电压电荷泵的PLL频率合成器

ADF4113HV整数分频频率合成器是专门为那些需要宽频率调谐范围和高调谐电压（15V）的压控振荡器（VCO）的应用而设计的。其工作在200MHz～4GHZ频率范围，供电电压为2．7～5．5V。该器件包括一个低噪声鉴相器（PFD）、一个高精度的高电压电荷泵、一个可编程参考分频器、可编程A计数器和B计数器，以及一个双模预置分频器（P／P＋1）。     

频率合成器的相位噪声分析

频率合成器被喻为雷达电子系统的"心脏",其相位噪声对设备和系统的性能影响很大.文中简单介绍了频率合成器相位噪声的基本概念.基于频率合成器的基本实现方法,分析了频率合成器中的相位噪声,通过实例说明了不同合成方式频率合成器的相位噪声.时频率合成器的低相噪声设计的工程实现有一定的指导意义.     

集成L波段VCO的频率合成器设计

从频率合成器的构成和噪声模型入手,分析了主要单元电路对噪声的贡献,进而研究了各频率合成器模块中的噪声影响因子,建立了不同模块的噪声模型,并在模型基础上改进了压控振荡器的电流源结构及鉴相器的延时单元电路,从而提高了频率合成器的噪声性能。根据上述方法,采用0.18μm射频CMOS工艺设计实现了一款低功耗、低噪声的频率合成器,经测试,核心电压1.8 V,功耗54 m W,带内噪声达到了-98 d Bc/Hz。测试结果表明噪声指标达到了国外同类产品水平,为设计和研发高集成度的射频收发系统芯片提供了很好的参考。     

一种9.8-mW 1.2-GHz CMOS 低噪声正交输出频率综合器

实现了一种基于标准0.18µm CMOS工艺的应用于北斗导航射频接收机的1.2GHz频率综合器。在频率综合器中采用了一种基于分布式偏置技术实现的低噪声高线性LC压控振荡器和一种基于源极耦合逻辑的高速低开关噪声正交输出二分频器,集成了基于与非触发器结构的高速8/9双模预分频器、无死区效应的延迟可编程的鉴频鉴相器和电流可编程的电荷泵。该频率综合器的输出频率范围从1.05到1.30GHz。当输出频率为1.21GHz 时,在100-kHz和1-MHz的频偏处相位噪声分别为-98.53dBc/Hz和-121.92dBc/Hz。工作电压为1.8V时,不包括输出Buffer的核心电路功耗为9.8mW。北斗射频接收机整体芯片面积为2.41.6 mm2。     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

UHF宽带数字频率合成器的设计

频率合成器在现代电子系统中应用日益广泛,UHF（超高频）宽带数字频率合成器是地囿数字电视广播覆盖网的重要设备——数字电视激励器和转发器中的主要组成单元。提出了一种UHF宽带小频率步进、低相噪数字频率合成器的设计方法,介绍了系统各部分的设计方法、器件选择、相关参数的计算及PCB（印制电路板）设计,最后给出了系统射频输出信号相噪测试结果,验证了本设计方法的有效性和设计方案的可行性。     

一种降低频率合成器相位噪声的高增益电荷泵

设计了一款低噪声高增益电荷泵,主要用于低相位噪声的频率合成器.在传统的电流转向型电荷泵结构中增加了非镜像结构的低噪声电流源单元,使电荷泵的输出电流呈比例增加,降低电荷泵对频率合成器输出相位噪声的贡献,以进一步降低频率合成器的相位噪声.采用0.18 μm SiGe BiCMOS工艺进行了设计仿真和流片验证.测试结果表明:频率合成器工作在频率为10 GHz时,电荷泵中高增益低噪声电流源关闭和开启情况下,锁相环相位噪声分别为-106.1 dBc/Hz@10 kHz和-108.68 dBc/Hz@10 kHz.实现了通过开启电荷泵中高增益低噪声电流源使锁相环输出相位噪声下降约3 dB的目标.     

一种低噪声快速转换频率合成器的设计与实现

介绍了一种低相位噪声、快速转换频率合成器的设计与实现,采用DDS、变带宽、频率预置等多种措施,频率转换时间〈80μs,并对实验结果进行了分析讨论。实验结果表明,该合成器相位噪声具有良好、锁定时间短,适合在超短波电台中应用。     

A dual-band frequency synthesizer for CMMB application with low phase noise

A wide-band frequency synthesizer with low phase noise is presented.The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range.This PLL is fabricated with 0.35μm SiGe BiCMOS technology.The measured result shows that the RMS phase error is less than 1°and the reference spur is less than -60 dBc.The proposed PLL consumes 20 mA cu...     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

一种X波段低相噪跳频源的设计

基于小数分频锁相环HMC704LP4设计了一种X波段跳频源,具有相位噪声低、杂散低、体积小的特点。针对指标要求拟定设计方案,简述设计过程,给出设计参数,对关键指标进行分析仿真,并给出测试曲线。     

A 8.75-11.2-GHz,low phase noise fractional-N synthesizer for 802.11a/b/g zero-IF transceiver

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented.The mathematical models for the behavior of the synthesizer’s spur and phase noise are analyzed,and the optimization methodology is proposed.Measurement results exhibits that the frequency synthesizer’s integrated phase noise is less than 1°(1 kHz to 100 MHz)with a 4.375 GHz carrier(after divide-by-2),and the reference frequency spur is below-60 dBc operating with a 33 MHz reference clock.The frequency synthesizer is fabricated on a standard 0.13μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.     

超宽带低相噪频率合成器的实现

介绍了1种频率范围4~16GHz,步进1MHz的超宽带、小步进、低相噪频率合成器的实现方法。通过混频式锁相环方案,大大降低了环内分频比,选用低相噪器件,以及采用了梳状谱发生器代替传统的大步进环等措施,使输出实现了低相噪指标。在16GHz输出时,相位噪声指标小于-90dBc/Hz(@10kHz)。并通过对合成器指标的分析,阐述了在混频环设计过程中需要注意的一些问题。     

一种先进的N分数锁相环频率合成器

分析了N分数PLL频率合成器，并把 Σ-Δ调制技术应用于频率合成器中，解决了频率分辨率和鉴相器工作频率之间的矛盾，同时大大提高了噪声性能。     

一种用于认知无线电的快速频率合成器设计

为了研制一种锁定时间短、相位噪声低、杂散抑制度高的频率合成技术,采用了直接数字式频率合成器(DDS)驱动锁相环(PLL)的结构。该频率合成器综合了DDS频率转换速度快、频率分辨率高和PLL输出频带宽、输出杂散低的优点。基于该结构研制实现了输出频率范围为700～800 MHz的宽带频率合成器,实验结果表明该频率合成器扫描模式Δf=1 MHz锁定时间不超过20μs,跳频模式Δf=50 MHz的定时间不超过30μs,近端杂散抑制度优于-50 dBc。     

An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer

Although some papers have qualitatively analyzed the effect of charge pump mismatch on phase noise and spurs in sigma-delta fractional-N frequency synthesizer, few of them have addressed this topic quantitatively. An analytical model is proposed in this paper to describe the behavior of charge pump mismatch and the corresponding phase noise. Numerical simulation shows that this model is of high accuracy and can be applied to the analysis of in-band phase induced by the charge pump mismatch in sigma-delta fractional-N PLL frequency synthesizer. Most importantly, this model discloses that 6 dB reduction of in-band phase noise due to charge pump mismatch can be achieved by halving the charge pump mismatch ratio. After studying the typical topologies of sigma-delta modulators (SDM), we proposed some strategies on the selection of SDM in frequency synthesizer design. Our analytical model also indicates that eliminating the charge pump mismatch is one major path towards the in-band phase noise reduction of the sigma-delta frequency synthesizer. Xiaojian Mao was born in Jiangsu Province, China, in 1978. He received the B.S. degree in electronic engineering from Jilin University, Changchun, China, in 2000. He is currently pursuing the Ph.D. degree in circuits and systems at Department of Electronic Engineering of Tsinghua University, Beijing, China. His current research includes frequency synthesizers and phase-locking and clock recovery for high-speed data communications. And His PhD thesis title is “Design and Analysis of Sigma-Delta Fractional-N PLL Frequency Synthesizer.” Huazhong Yang received BS, MS, and PhD Degrees in electronics engineering from Tsinghua University, Beijing, in 1989, 1993, and 1998, respectively. He is a Professor and Head of the Circuits and Systems Division in the Department of Electronic Engineering at Tsinghua University, Beijing. His research interests include CMOS radio-frequency integrated circuits, VLSI system structure for digital communications and media processing, low-voltage and low-power circuits, and computer-aided design methodologies for system integration. He has authored and co-authored 6 books and more than 100 journals and conference papers. He was the winner of Chinas National Palmary Young Researcher Award in 2000. Hui Wang received the B.S. degree from Department of Radio Electronics, from Tsinghua University, Beijing, China. She was a visiting scholar at Stanford University, CA, USA from February 1991 to September 1992. Currently she is a Professor of the Circuits and Systems Division in the Department of Electronic Engineering and the deputy dean of academic affairs office at Tsinghua University, Beijing, China. Her research interests include modeling and simulation of radio-frequency CMOS integrated circuits, automatic design methodology for low voltage and low-power integrated circuits, and interconnect modeling and synthesis for deep submicron system-on-a-chip. She has authored and co-authored 4 books and over 70 papers. She was a primary research of TADS-C4 which gained a third-grade prize for the national progress in science and technology in China in 1993.     

3.1~4.9 GHz宽带低相位噪声频率源的研制

基于LTC6946-2频率合成器设计了3.1~4.9 GH频率源,给出了参数设计过程和实物测试结果。该频率源具有宽带、低相位噪声、低杂散、低成本和占用面积小等特点。经过硬件调试达到的主要指标为:输出频率3.1~4.9 GHz,步进10 MHz,相位噪声优于-97.8 dBc/Hz@1 kHz和-99.3 dBc/Hz@10 kHz,杂散优于-90 dBc。     

一种低附加相位噪声的频率合成方法

频率源的相位噪声水平直接制约雷达的性能上限,因而低相噪频率合成技术是高性能雷达系统的一项关键技术。现有低相噪频率合成方法常用高次倍频实现,整体性能上严重依赖于低相噪晶振,成本一直居高不下。对此,提出一种低附加相位噪声频率合成方法,即采用最小化链路上附加相位噪声的技术,用普通恒温晶振级联低相噪放大器、梳状谱发生器和锁相环,最终实现低相位噪声的频率合成。实测数据表明,本文方法以100 MHz普通恒温晶振为参考,积分区间[1 kHz, 30 MHz]的时间抖动为11 fs,频率合成在5.8 GHz载波的相位噪声为-119 dBc/Hz@1 kHz,积分区间[1 kHz, 30 MHz]的时间抖动为13.7 fs,总附加时间抖动为8.17 fs,附加相位噪声仅1.9 dB,达到了业界领先水平,能够有效提升毫米波雷达系统的成像性能,优于传统频率合成方法。