一种新型高压场致发光驱动电路的设计

提出了一种横向高压敏感功率器件的结构，采用SENSE技术制作末端功率器件。该器件是一种新型敏感器件，利用其版图结构及在结终端技术中的特殊结构，可使场致发光(EL)的驱动、智能开关电源等的保护功能更加可靠。在EL控制和驱动电路中，采用一种新型误差放大电路和PWM电路，给出了电路模型参数，并设计了一种具有极低电磁干扰和高稳定度的新型EL电路。     

A CMOS compatible lateral emitter switched thyristor with enhancedturn-on capability

A new Lateral Emitter Switched Thyristor structure (LEST) is proposed and experimentally verified. The structure differs from the conventional LEST in that it embeds a floating ohmic contact between the n^- drift region and the n⁺ floating emitter. Both simulation and experimental results show that the device has an enhanced turn-on capability compared with the conventional LEST without deteriorating its other characteristics. The device is fabricated using a 3 μm CMOS process to have a 320 V breakdown voltage and a 0.7 V threshold voltage. Thyristor turn-on is observed at an anode voltage below 2 V. The maximum MOS controllable current density is in excess of 200 A/cm² with 5 V gate voltage     

Circuit techniques for a 1.8-V-only NAND flash memory

Focusing on internal high-voltage (V_pp) switching and generation for low-voltage NAND flash memories, this paper describes a V _(pp) switch, row decoder, and charge-pump circuit. The proposed nMOS V_pp switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the V _pp leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed V_pp switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and V_pp switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 μA. The proposed pump scheme reduced the area required for charge-pump circuits by 40%     

A new three-terminal thyristor-based high-power switchingconfiguration with high-voltage current saturation

A new high-voltage power switch configuration having thyristor based on-state current conduction together with high-voltage current saturation characteristics is described. Current saturation is obtained in the new thyristor structure by diverting part of the base current at a predesigned current level to bring the NPN and PNP transistors comprising the thyristor out of their regeneratively-coupled conduction mode. The concept has been experimentally verified by fabricating 1200 V, 175 A devices     

Complementary-SCR ESD protection circuit with interdigitatedfinger-type layout for input pads of submicron CMOS IC's

A new ESD protection circuit with complementary SCR structures and junction diodes is proposed. This complementary-SCR ESD protection circuit with interdigitated finger-type layout has been successfully fabricated and verified in a 0.6 μm CMOS SRAM technology with the LDD process. The proposed ESD protection circuit can be free of VDD-to-VSS latchup under 5 V VDD operation by means of a base-emitter shorting method. To compensate for the degradation on latching capability of lateral SCR devices in the ESD protection circuit caused by the base-emitter shorting method, the p-well to p-well spacing of lateral BJT's in the lateral SCR devices is reduced to lower its ESD-trigger voltage and to enhance turn-on speed of positive-feedback regeneration in the lateral SCR devices. This ESD protection circuit can perform at high ESD failure threshold in small layout areas, so it is very suitable for submicron CMOS VLSI/ULSI's in high-pin-count or high-density applications     

High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories

In order to scale high-voltage transistors for high-density negative-gate channel-erasing NOR flash memories, two circuit techniques were developed. A proposed level shifter with low operating voltage is composed of three parts, a latch holding the negative erasing voltage, two coupling capacitors connected with the latched nodes in the latch, and high-voltage drivers inverting the latch, resulting in reduction of the maximum internal voltage by 0.5 V. A proposed high-voltage generator adds a path-gate logic to a conventional high-voltage generator to realize both low noise and low ripple voltage, resulting in a reduction of the maximum internal voltage by 0.5 V. As a result, these circuit techniques along with high coupling-ratio cell technology can scale down the high-voltage transistors by 15% and can realize higher density negative-gate channel-erase NOR flash memories in comparison with the source-erase NOR flash memories.     

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

A reduced word-line voltage swing (RWS) circuit configuration that results in a high-speed bipolar ECL (emitter coupled logic) RAM is proposed. The write operation can be performed with the configuration in the condition of reduced word-line voltage swing, which causes write operation error in conventional circuit configurations. The proposed configuration cuts off the hold current of the selected memory cell, and then the low-voltage node is charged up through the load p-n-p transistor. A 16-kb ECL RAM with a p-n-p loaded memory cell was fabricated by advanced silicide-base transistor (ASBT) process technology. A 2-ns access time was obtained with 1.8-W power consumption in which the word-line voltage swing was reduced by 0.7 V from a conventional case. Simulation results show that the access time is improved by 25% compared with a conventional case. Simulation results also show that writing time becomes comparable with the conventional time of 1.7 ns when the load p-n-p transistor has a saturation current of 5.0× 10¹⁷ A and a current gain of 1.0. The saturation current is 5 times larger and the current gain is 5 times smaller than those of the standard lateral p-n-p transistor     

一种基于高压工艺的高精度电流采样电路

提出了一种用于大功率LED驱动芯片中的电流采样电路。采用电阻采样技术,运用高压、高增益、大带宽的运放,使采样电路具有高精度和快的响应速度。基于0.8μm 40 V BCD工艺,对提出的电流采样电路进行仿真验证。结果表明,在大功率应用下,该采样电路的采样精度高达99.68%,有很好的实用价值。     

电压瞬变对高压固态开关的影响

对于高压放电回路,高压开关是一个关键器件。高压放电回路中高压固态开关上电压可能出现瞬变,这种瞬变会引起高压固态开关的误触发或者击穿。开关的工作异常将导致整个放电回路的失效。本文从原理上分析了这种失效产生的原因,并且进行了电路仿真,通过仿真分析提出了如何去避免这种失效的发生,给出了相应的防护措施,最后通过实验验证了保护措施的有效性。     

A new Schmitt trigger circuit in a 0.13-/spl mu/m 1/2.5-V CMOS process to receive 3.3-V input signals

A new Schmitt trigger circuit, which is implemented by low-voltage devices to receive the high-voltage input signals without gate-oxide reliability problem, is proposed. The new proposed circuit, which can be operated in a 3.3-V signal environment without suffering high-voltage gate-oxide overstress, has been fabricated in a 0.13-/spl mu/m 1/2.5-V 1P8M CMOS process. The experimental results have confirmed that the measured transition threshold voltages of the new proposed Schmitt trigger circuit are about 1 and 2.5 V, respectively. The new proposed Schmitt trigger circuit is suitable for mixed-voltage input-output interfaces to receive input signals and reject input noise.     

A high-voltage IC for a transformerless trunk and subscriber line interface

A new high-voltage, junction-isolated, complementary bipolar technology has been used to fabricate an IC for a transformerless trunk and subscriber line interface. The new technology provides both vertical p-n-p and n-p-n transistors with BV/SUB CE0/ greater than 60 V, betas of 100, and f/SUB T/'s of 200 MHz. It permits the straightforward op amp realization of a new op amp circuit configuration in transformerless line circuits. The new configuration uses the high-voltage IC plus some low voltage control circuitry to provide limited current battery-feed, loop-closure detection, reverse-battery signaling, two-wire to four-wire conversion, lightning protection, power-down capability, and longitudinal performance which is independent of the battery-feed current magnitude.     

A gate-coupled PTLSCR/NTLSCR ESD protection circuit fordeep-submicron low-voltage CMOS ICs

A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit     

新型多路输出数字调压电路的设计

研究了一种新型多路输出数字调压电路。以FPGA为核心,利用其丰富的I/O口,实现多路电压同时输出。待转换的数据经USB2.0接口输入FPGA内部FIFO中,减少电压配置时间。采用高压运放芯片,工作于非对称供电模式。实验结果表明,电压调节范围-39V~+49.95V,步进调节灵敏度为0.0244V,最大输出电流50mA,纹波电压小于2mV。     

一种注入增强型快速SOI-LIGBT新结构研究

薄顶层硅SOI(Silicon on Insulator)横向绝缘栅双极型晶体管(Lateral Insulated-Gate Bipolar Transistor,LIGBT)的正向饱和电压较高,引入旨在减小关断态拖尾电流的集电极短路结构后,正向饱和电压进一步增大。提出了一种注入增强型(Injection Enhancement,IE)快速LIGBT新结构器件(F-IE-LIGBT),并对其工作机理进行了理论分析和模拟仿真验证。该新结构F-IE-LIGBT器件整体构建在薄顶层硅SOI衬底材料上,其集电极采用注入增强结构和电势控制结构设计。器件及电路联合模拟仿真说明:新结构F-IE-LIGBT器件在获得较小正向饱和电压的同时,减小了关断拖尾电流,实现了快速关断特性。新结构F-IE-LIGBT器件非常适用于SOI基高压功率集成电路。     

High-Voltage Analog System for a Mobile NAND Flash

High-voltage analog circuits, including a novel high-voltage regulation scheme, are presented with emphasis on low supply voltage, low power consumption, low area overhead, and low noise, which are key design metrics for implementing NAND Flash memory in a mobile handset. Regulated high voltage generation at low supply voltage is achieved with optimized oscillator, high-voltage charge pump, and voltage regulator circuits. We developed a design methodology for a high-voltage charge pump to minimize silicon area, noise, and power consumption of the circuit without degrading the high-voltage output drive capability. Novel circuit techniques are proposed for low supply voltage operation. Both the oscillator and the regulator circuits achieve 1.5 V operation, while the regulator includes a ripple suppression circuit that is simple and robust. Through the paper, theoretical analysis of the proposed circuits is provided along with Spice simulations. A mobile NAND Flash device is realized with an advanced 63 nm technology to verify the operation of the proposed circuits. Extensive measurements show agreement with the results predicted by both analysis and simulation.     

A Novel Latch-Up Protection for Bulk-Silicon Scan Driver ICs of Shadow-Mask Plasma-Display Panel

This letter reports a low-cost and excellent latch-up protection technology for bulk-silicon scan driver ICs of shadow-mask plasma-display panel (SM-PDP) by integrating a 100-V lateral double-diffused (LD) MOS and a standard low-voltage (LV)-CMOS control circuit. The technology is implemented using an N+ guard ring in the LV-n-well, a P+ guard ring in the p-substrate near the LV-nMOS, and a deep high-voltage (HV)-n-well and a p-drift guard ring between the HV-nLDMOS and LV-CMOS circuits. The experiment results show that the latch-up in the LV-CMOS circuits is avoided when the scan ICs are applied with -340 V during the sustain periods.     

用雪崩三极管电路生成高压负脉冲技术研究

雪崩效应因为能在极短时间内输出极大电流,常被用来设计高压脉冲电路。分析了利用雪崩三极管电路生成高压正脉冲的实现方案,并提出了改进的设计,接着分析了脉冲输出过程中负载回路的电流流向,通过改变信号输出点,设计了输出高压负脉冲的电路。电路输出的脉冲幅度达到了-200V,前沿约3.2ns。与相似结构的正脉冲电路相比,性能略有降低。同时对性能下降的原因进行了分析。     

CMOS four-quadrant analogue multiplier for RF applications

A CMOS four-quadrant multiplier consisting of four MOS transistors operating in the saturation region is introduced. The circuit exploits the quadratic relation between the current and voltage of the MOS transistor in saturation. Simulation results show that, for a supply voltage of 1.2 V multiplication can be performed at a frequency of 1.8 GHz, achieving better performances than a recently proposed similar architecture     

A CMOS integrated driver for incandescent lamps with output power control

An integrated protection circuit to be used as a part of an intelligent power switch is presented in this paper. The circuit is designed to address the overcurrent solicitation due to incandescent lamp loads, typical in industrial and automotive environment. The circuit realizes, with a nonlinear feedback loop, an on-off switching of the load voltage as a function of the value of the load current, with the aim of keeping its mean value constant. This mechanism allows an efficient power transfer to the load, by minimizing the power dissipated on the MOS switch. Simulations and experimental measurements, carried out on a prototype chip fabricated with a 2-/spl mu/m CMOS high-voltage (50 V) process, are also shown.     

A power IC technology with excellent cross-talk isolation

This paper reports a low-cost, excellent cross-talk isolation power integrated circuit (PIG) technology capable of integrating high-voltage LDMOS, high-voltage LIGBT, and low-voltage CMOS control circuit. The technology is implemented using a conventional twin-well CMOS process with no compromise on the CMOS devices, and the breakdown voltages of the LDMOS and LIGBT with drift length of 40 μm are over 400 V. Using this technology, operating current of the body diode of the LDMOS can be improved by over 16 times and operating current of the LIGBT can be improved by over five times before CMOS latch-up in the control circuit occurs