0.18 μm 1.8 V 10 bit 100 MS/s CMOS电流舵D/A IP设计与验证

基于GSMC 0.18μm CMOS工艺,采用曲率补偿带隙参考电压源和中心对称Q2随机游动对策拓扑方式的NMOS电流源阵列版图布局,实现了一种10 bit 100 MS/s分段温度计译码CMOS电流舵D/A转换器.当电源电压为1.8 V时,D/A转换器的功耗为10 mW,微分非线性误差和积分非线性误差分别为1 LSB和0.5 LSB.在取样速率为100 MS/s,输出频率为5 MHz条件下,SFDR为70 dB,10 bit D/A转换器的有效版图面积为0.2 mm2,符合SOC的嵌入式设计要求.     

12位80MHz采样率具有梯度误差补偿的CMOS电流舵D/A转换器实现

提出了一种12位80MHz采样率具有梯度误差补偿的电流舵D/A转换器实现电路.12位DAC采用分段式结构,其中高8位采用单位电流源温度计码DAC结构,低4位采用二进制加权电流源DAC结构,该电路中所给出的层次式对称开关序列可以较好地补偿梯度误差.该D/A转换器采用台湾UMC 2层多晶硅、2层金属(2P2M)5V电源电压、0.5μm CMOS工艺生产制造,其积分非线性误差小于±0.9LSB,微分非线性误差小于±0.6LSB,芯片面积为1.27mm×0.96mm,当采样率为50MHz时,功耗为91.6mW.     

一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核

采用低摆幅低交叉点的高速CMOS电流开关驱动器结构和中心对称Q2随机游动对策拓扑方式的pMOS电流源阵列版图布局方式,基于TSMC 0.18靘 CMOS工艺实现了一种1.8V 10位120MS/s分段温度计译码电流舵CMOS电流舵D/A转换器IP核.当电源电压为1.8V时,D/A转换器的微分非线性误差和积分非线性误差分别为0.25LSB和0.45LSB,当采样频率为120MHz,输出频率为24.225MHz时的SFDR为64.9dB.10位D/A转换器的有效版图面积为0.43mm×0.52mm,符合SOC的嵌入式设计要求.     

一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核

采用低摆幅低交叉点的高速CMOS电流开关驱动器结构和中心对称Q2随机游动对策拓扑方式的pMOS电流源阵列版图布局方式,基于TSMC 0.18靘 CMOS工艺实现了一种1.8V 10位120MS/s分段温度计译码电流舵CMOS电流舵D/A转换器IP核.当电源电压为1.8V时,D/A转换器的微分非线性误差和积分非线性误差分别为0.25LSB和0.45LSB,当采样频率为120MHz,输出频率为24.225MHz时的SFDR为64.9dB.10位D/A转换器的有效版图面积为0.43mm×0.52mm,符合SOC的嵌入式设计要求.     

一种用于触摸屏SoC的10位200kS/s SAR ADC IP核

采用“5MSBs (Most-Significant-Bits) + 5LSBs (Least-Significant-Bits)”C-R混合式D/A转换方式以及低失调伪差分比较技术,结合电容阵列对称布局以及电阻梯低失配版图设计方法,基于0.18µm 1P5M CMOS Logic工艺,设计实现了一种用于触摸屏SoC (System-on-Chip)的8通道10位200kS/s逐次逼近型A/D转换器IP核。在1.8V电源电压下,测得的微分非线性误差和积分非线性误差分别为0.32LSB和0.81LSB。在采样频率为200kS/s,输入频率为91kHz时,测得的无杂散动态范围(SFDR: Spurious-Free Dynamic Range)和有效位数(ENOB: Effective-Number-of-Bits)分别为63.2dB和9.15bits,功耗仅为136µW。整个A/D转换器IP核的面积约为0.08mm2。设计结果显示该转换器满足触摸屏SoC的应用要求。     

10bit 200MHz采样率具有梯度误差补偿的CMOS视频D/A转换器实现

提出了一种10bit 200MHz采样率具有梯度误差补偿的CMOS视频D/A转换器实现电路。采用分段式结构,利用层次式对称开关序列消除由热分布不均所引起的对称误差。该DAC集成在一款视频自适应均衡芯片中,整个芯片采用Charted 3.3V电压、0.35μm CMOS工艺生产制造。DAC的面积为1.26mm×0.78mm,工作在4Fsc(14.318MHz)采样频率时,其有效数据比特为9.3个,其积分非线性误差和微分非线性误差均小于±0.5LSB。     

16位逐次逼近A/D转换器熔丝误差修调技术

提出了一种提高16位逐次逼近(SAR)A/D转换器精度的熔丝误差修调技术。该技术用于提高A/D转换器内部核心模块—16位DAC的精度,从而达到提高整个A/D转换器精度的目的。电路采用标准CMOS工艺流片。测试结果显示,熔丝误差修调后,常温下,电路的INL为2.5 LSB,SNR为88.8 dB,零点误差EZ为1.1 LSB;修调后,A/D转换器有效位数ENOB从12.56位提高到14.46位。     

基于BiCMOS技术的高速数字/模拟转换器

基于BiCMOS技术,进行了高速数字/模拟转换器研究.以并行输入类型,电流工作模式的16位D/A转换器为载体,进行了电路设计、工艺制作和测试.在±5.0V工作电压下,测试得到转换速率≥30MSPS,建立时间为50ns,增益误差为±8%FSR,积分非线性误差为1/2 LSB,功耗为500mW.     

基于BiCMOS技术的高速数字/模拟转换器

基于BiCMOS技术,进行了高速数字/模拟转换器研究.以并行输入类型,电流工作模式的16位D/A转换器为载体,进行了电路设计、工艺制作和测试.在±5.0V工作电压下,测试得到转换速率≥30MSPS,建立时间为50ns,增益误差为±8%FSR,积分非线性误差为1/2 LSB,功耗为500mW.     

一种14位400MS/S分段型电流舵DAC的设计

基于TSMC O.25μm CMOS工艺,采用分段开关电流结构,设计了一种基于2.5 V电源电压的14位400MS/s D/A转换器.该D/A转换器内置高精度带隙基准源、高速开关驱动电路和改进的Cascode单位电流源电路,以提高性能.D/A转换器的积分非线性(INL)和微分非线性(DNL)均小于0.5 LSB.在400 MHz采样频率、199.8 MHz输出信号频率时,其无杂散动态范围(SFDR)达到85.4 dB.     

一种用于暗光环境下的CMOS图像传感器的非线性模数转换器

从优化算法、硬件结构和模拟结果入手,通过对CMOS图像传感器暗光环境下模数转换电路的优化设计,提出了一种暗光环境下性能提升的大动态范围非线性模数转换器的设计.在模拟电路模块完成了暗光优化图像处理算法,使暗光环境下光电转换数字码密度增大,在不增加额外芯片面积和功耗的同时,提高了CMOS图像传感器的暗光图像性能.     

A power-adaptable A/D converter with integrated data compression

A novel adaptable analog/digital converter (ADC) that combines analog/digital conversion and entropy-coding for integrated data compression and low-power operation is reported. The converter has high flexibility of operation in terms of adaptable resolution, conversion rate and input signal statistics. This feature allows to adaptively react to changes of the situation and to put the device in each case into the optimum configuration. The ADC has been realized in a 0.6 μm CMOS technology with a peak resolution of 12 bit and 200 kS/s maximum sampling rate. A comprehensive power model of the converter is presented that reflects precisely the power consumption determined from experiments. The model is very useful for optimizing the converter configuration in the node of a wireless sensor network for specific situations. A feasible real-life application is demonstrated.     

一种流水线结构A／D转换器的设计

介绍了一种适于数字ＣＭＯＳ工艺实现的优化流水线结构Ａ／Ｄ转换器的设计。并从如何减少误差来源，消除误差影响，减小电路设计难度等方面对该结构进行了详细分析。公式论证和仿真结果表明，采用该方案可实现２０ＭＨｚ工作频率和１０位分辨率的高速高精度、低功耗Ａ／Ｄ转换器。     

A CMOS 6-b, 400-MSample/s ADC with error correction

A CMOS 6-bit 400-MSample/s (MS/s) flash analog/digital converter (ADC) using an additional comparator for background autozeroing has been developed. Additionally, an error-correction technique detects and corrects errors after thermometer code zero-to-one transition detection, improving the error rate from 10E-4 to 10E-8 at 400 MS/s with a 200-MHz analog input. This ADC was fabricated in a single-poly, double-metal, 0.35-μm CMOS technology and occupies 1.6×0.75 mm. The power consumption is 190 mW at 400 MS/s with 3.0 V power supply. This ADC has a two-clock cycle latency     

A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC

A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 mum CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm², and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.     

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.     

基于控阈技术的电流型CMOS多值ADC电路设计

本文利用传输电流开关理论对多值A／D转换器进行了理论分析，设计了基于数字电路设计理论中控阈技术的电流型CMOS多值A／D转换器电路，计算机模拟表明该电路设计具有正确的逻辑功能。利用该设计方法可避免模拟信号的复杂处理，显著地简化了电路结构，提高了A／D转换的信息密度。     

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented.The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter,which are based on well-designed calibration reference, calibration DAC and comparators.The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.     

A 12-bit, 1-MHz, two-step flash ADC

A monolithic 12-b 1 MHz, two-step flash analog-to-digital converter (ADC) has been implemented in standard 3-μm CMOS technology. A 12-b accurate reference bank incorporating a switched-capacitor integrator and a bank of 66 sample-and-hold amplifiers is discussed. Self-calibration techniques are used to correct for the converter offset, gain, and nonlinearity errors. The converter differential nonlinearity errors below 1/2 LSB and the S/(N+D) signal to noise is 70 dB for 100-kHz analog input     

A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2with mixed-signal chopping and calibration

This paper describes a two-step analog-to-digital converter (ADC) with a mixed-signal chopping and calibration algorithm. The ADC consists primarily of analog blocks, which do not suffer from the matching limitations of active devices. The offset on two residue amplifiers limits the accuracy of the ADC. Background digital offset extraction and analog compensation is implemented to continuously remove the offset of these critical analog components. The calibrated two-step ADC achieves -70 dB THD in the Nyquist band, with a 2.5-V supply. The ADC is realized in standard single-poly 5-metal 0.25-μm CMOS, measures 1.0 mm² , and dissipates 295 mW