Rapid low-resistance interconnects by selective tungsten deposition on laser-direct-written polysilicon

Polysilicon interconnections were locally deposited on oxide-covered silicon wafers by pyrolysis of silane using a scanned Ar+-laser spot. The 2-µm-wide interconnects, written at scan speeds of 2.5 mm/s, have a 500-µΩ.cm resistivity and exhibit low contact resistance to underlying Al and Al/Si structures. These films were subsequently reacted with WF6vapor to form a tungsten-silicon composite interconnect by the silicon reduction of WF6. Electrical tests show that the conductivity of 0.4-µm-thick conductors is enhanced up to 20-fold, by formation of a surface metallic layer having conductivity characteristic of pure thin-film tungsten. Auger and Rutherford backscattering spectra (RBS) confirm the purity and selectivity of the surface tungsten layer formed at temperatures compatible with preexisting aluminum metallization. The tungsten-polysilicon composite interconnects have applications as rapidly written discretionary metallization for prototyping and in situ analysis of integrated circuits.     

One-gate-wide CMOS Inverter on laser-recrystallized polysilicon

A CMOS inverter having a single gate for both n and p channel devices has been fabricated using bulk silicon for the p channel device and a laser-recrystallized silicon film for the n channel device. The fabrication details and dc electrical performance of this device are described.     

SATPOLY: a self-aligned tungsten on polysilicon process for CMOSVLSI applications

The use of complementarily doped n⁺ and p⁺ polysilicon has been proposed for future generations of CMOS technology. The implementation of this technology requires low-resistance shunts both to reduce the overall resistance of the gate level interconnections and to short out the polysilicon p-n junctions. A process in which tungsten is chosen to provide the low-resistance shunts, with the necessary gate sidewall spacers formed before the selective deposition of tungsten, is described. A nonselective tungsten deposition process, originally developed explicitly for the implementation of direct tungsten gate MOS technology, is a key step in the formation of the spacers in the SATPOLY (self-aligned tungsten on polysilicon) process. The work function stability and the adhesion of the tungsten-polysilicon double-layer structure as a function of the polysilicon glue layer thickness have also been investigated     

Experimental characterization of the diode-type polysilicon loadsfor CMOS SRAM

Experimental characterization of the diode-type n⁺-p-n ⁺ poly-Si loads for SRAM applications demonstrates that the resistance of the structure and its response to the bit-line voltages are dominated by such properties of the parasitic thin-film transistor associated with this device as fixed positive charge and `gate' oxide thickness. Topographical effects observed in this study are interpreted in terms of the thickness variation of a dielectric overlaying the poly-Si feature and the fixed positive charges present in this dielectric in the vicinity of the poly-Si surface     

Design, measurement and analysis of CMOS polysilicon TFToperational amplifiers

The small signal properties of polysilicon TFT opamps have been investigated in this paper. A method for the scaling of g_m (transconductance) and g_ds (output conductance) has been proposed, facilitating their estimates for various transistors in operational amplifiers. The analysis of two CMOS opamps fabricated by a low temperature, glass compatible poly-Si TFT process is demonstrated in comparison to the measured performance. The first implementation has been internally compensated with high load-driving capability (up to 36 pF), while the second one has employed a cascode stage for increased gain (56 dB)     

Effects of different tungsten polycide process on the effectivechannel length and performance of deep submicron CMOS transistors

The effects of different tungsten polycide technologies on the effective channel length and electrical performance of scaled CMOS transistors fabricated by rapid thermal annealing (RTA) have been investigated. Contrary to previous studies, it is found that the sputtered WSi_x device produces a larger reduction in channel length, a result which is confirmed by gate-to-drain overlap capacitance C_GD measurement. Experiments also indicate that the sputtered WSi_x devices possess a lower driving ability, and have higher off state leakage not only for the short channel but also for the long channel range     

基于W双十字形微结构的太阳能选择性吸收薄膜的数值研究

提出一种基于金属-介质六层膜的高太阳辐射吸收的新型双十字形微结构,计算显示其加权平均吸收率在截止波长前的光谱区约为96.5%,850K温度的辐射率为0.086.通过场图分析对太阳能波段的光热吸收机制进行了探讨.不同入射角情况下的计算结果显示,基于双十字形微结构的太阳能选择性吸收薄膜可具有低偏振依赖性,以及小于50°入射角条件下的低入射角依赖性特点,将能够满足太阳能选择性吸收器件的应用需求.     

Activation of polysilicon connections by selective CW laser annealing

A new self-aligned procedure has been developed to connect polysilicon links on chip by using a CW argon laser. A silicon nitride mask serves as a diffusion barrier over part of the link during doping of the polysilicon, and later as an antireflection coating to couple the maximum amount of light into the undoped region during laser scanning. The laser melts this region only and dopant atoms rapidly diffuse in from the neighboring parts of the link. For the optimum mask length, 100 percent of the links were open circuits ( >15 MΩ) before irradiation, while the sheet resistivity was reduced to 12 Ω after processing.     

Effect of deposition temperature on LPCVD polysilicon

The electrical properties of LPCVD silicon are shown to be optimised for microelectronic applications by depositing the films as an amorphous layer and annealing to yield a polycrystalline form. The film resistivity is lowered and the piezoresistive coefficient raised by this technique. These improvements are explained by a simple theory which incorporates trap density and grain size effects and also allows the temperature coefficients of resistance and gauge factor to be calculated.     

Scaling of nanocrystal memory cell by direct tungsten bitline on self-aligned landing plug polysilicon contact

This letter reports the first full process integration of nanocrystal memory cell with 4.6 F/sup 2/ area ( NOR type), which is achieved by direct tungsten (W) bitline on self-aligned landing plug polysilicon contact. Prior to the nanocrystals (NCs) formation, surface hydroxylation of the tunnel SiO/sub 2/ by exposure to 1:99 hydrogen flouride (HF) is performed to maintain controllability of NCs. Also, the degradation of the tunnel SiO/sub 2/ caused by HF dipping is overcome to some extent through its fluorination. Robust four-threshold voltage (V/sub th/) states for 2-bit operation per cell are observed due to the localized injected charge and V/sub th/ asymmetry from different reading sensitivity to localized charges.     

Effect of Hydrogen implantation on polysilicon p-n junctions

The effect of hydrogen implantation on theI(V)characteristics of lateral polysilicon p-n junctions is reported. After implantation with hydrogen and annealing at 400°C, a moderate decrease in the forward current and a large decrease in the reverse current is observed. In addition, the reverse breakdown voltage is increased. Best results were obtained for hydrogen dose of 10¹⁶cm^-2. The measurements are explained by considering both electric field enhancement of emission and capture rates and the generation of new trap levels by ion implantation.     

NCMOS: a high performance CMOS logic

CMOS has been the mainstay technology for VLSI design for the last several years. However, recently, BiCMOS technology has been proposed for speed critical applications. In this paper we propose a new circuit structure called NCMOS, which employs a low Vt NMOS transistor in place of the bipolar transistor, and provides significantly higher speed than a conventional CMOS design. This is realized at the cost of only one extra masking step, compared to 4-5 extra masks for a full BiCMOS process     

Accurate determination of ultrathin gate oxide thickness andeffective polysilicon doping of CMOS devices

We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 Å) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments     

CMOS电容式湿度传感器特性研究

提出了一种CMOS电容式湿度传感器特性研究方案.研究所用的微电容湿度传感器由标准CMOS工艺结合MEMS 后处理技术加工而成.为了测试湿度传感器的响应时间,设计了一种响应时间测试装置.测试结果表明,该电容式湿度传感 器在相对湿度25％～95％的范围内具有较好的线性度;其回滞在75％RH时达到最大,为2％ RH;该传感器...     

High performance low temperature polysilicon thin film transistorusing ECR plasma thermal oxide as gate insulator

Electron cyclotron resonance (ECR) plasma thermal oxide has been investigated as a gate insulator for low temperature (⩽600°C) polysilicon thin-film transistors based on solid phase crystallization (SPC) method. The ECR plasma thermal oxide films grown on a polysilicon film has a relatively smooth interface with the polysilicon film when compared with the conventional thermal oxide and it shows good electrical characteristics. The fabricated poly-Si TFT's without plasma hydrogenation exhibit field-effect mobilities of 80 (60) cm²/V·s for n-channel and 69 (48) cm²/V·s for p-channel respectively when using Si₂ H₆(SiH₄) source gas for the deposition of active poly-Si films     

Effects of hydrogenation on the performance and hot-carrierendurance of polysilicon thin-film transistors

Statistical analysis was performed to investigate the performance and reliability of hydrogenated polysilicon thin-film transistors (TFTs) in relation to the hydrogenation process. The hydrogenation was performed in pure H₂ plasma and in plasma of 4% H₂ diluted in Ar or He gas. TFTs hydrogenated in H₂/Ar or H₂/He plasma have lower on-voltage and better uniformity compared to the nonhydrogenated devices due to passivation of grain boundary dangling bonds. Hot-carrier experiments demonstrate that electron trapping is the dominant mechanism at the early stages of the degradation process and generation of interface and grain boundary traps as the stress proceeds further. The overall results indicate that devices hydrogenated in H₂/He plasma are the most reliable in terms of uniformity and hot-carrier stress     

Frequency limitations on broad-band performance of shunt slotarrays

Two methods are presented for the analysis of slot array performance as a function of frequency, taking mutual coupling into account. The first is a direct method, the other an iterative one. These are applied to a seven-slot resonant array and to a 21-slot traveling wave array. This analysis permits prediction of the bandwidth and provides comprehension of broadband limitations. The two examples presented show good agreement between theory and measurement     

Effect of laser recrystallization of polysilicon on the underlying substrate

Although laser recrystallization of polysilicon into a large-grain structure degrades the lifetime in the underlying substrate, a subsequent heat treatment similar to that seen during transistor fabrication increases the lifetime to approximately the value in the regions not laser processed. No electrical effects of laser damage to the underlying substrate are found in the transient behavior of MOS capacitors after furnace annealing or in the properties of p⁺n junction diodes. Since any damage to the substrate during laser processing is substantially eliminated by subsequent heat cycles, recrystallization is compatible with fabrication of high-quality devices in the substrate.     

The limiting performance of a CMOS bistable register based on waveform considerations

The fundamental latching behaviour of a CMOS bistable register is described. The circuit response of two cross coupled NAND gates being driven by a data and a clock signal can be decomposed into four individual regions of operation. Closed form small signal solutions for each region of operation are described and favourably compared with SPICE. The third region of operation contains the closed loop regenerative mode of operation inherent to the bistable NAND gate configuration and fundamental to the latching behaviour of a register. From these results, necessary and sufficient conditions for latching data into a bistable register are developed. Finally, from these necessary and sufficient conditions, the limiting condition for latching is presented and verified by SPICE.