共查询到20条相似文献,搜索用时 93 毫秒
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高压变频器的散热与通风质量的好坏直接关系到设备的可靠性。本文介绍了高压变频器散热与通风设计过程及相关的原理,以及一些值得关注的问题。并提出了在高压变频器的散热与通风设计过程中的一些新的建议。 相似文献
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对矿用变频器主电路器件损耗做了分析,根据隔爆腔体结构,设计出了强制循环风冷散热。实验表明,该散热设计使变频器具有很好的散热效果,可满足工业实际应用的要求。 相似文献
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在变频器的应用中,有些场合对变频器的体积要求很严格,例如纺织机械,要求变频器做成宽度很窄的"书本"式结构。这样就迫使变频器中散热器必须做特殊设计,增加了散热器设计和安装的难度,同时也增加了成本,影响了散热器的散热效果。泰科电子最新推出的flow90功率模块通过模块内部管脚和散热底板90o设计,很好地解决了这个问题。 相似文献
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散热问题是困扰矿用防爆变频器安全运行的难题.高性能矢量控制的重要任务就是提高变频器的控制精度。本文主要介绍合康防爆ZJT系列变频器在煤矿井下的应用情况。 相似文献
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Low-voltage-swing monolithic dc-dc conversion 总被引:1,自引:0,他引:1
Kursun V. Narendra S.G. De V.K. Friedman E.G. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2004,51(5):241-248
A low-voltage-swing MOSFET gate drive technique is proposed in this paper for enhancing the efficiency characteristics of high-frequency-switching dc-dc converters. The parasitic power dissipation of a dc-dc converter is reduced by lowering the voltage swing of the power transistor gate drivers. A comprehensive circuit model of the parasitic impedances of a monolithic buck converter is presented. Closed-form expressions for the total power dissipation of a low-swing buck converter are proposed. The effect of reducing the MOSFET gate voltage swings is explored with the proposed circuit model. A range of design parameters is evaluated, permitting the development of a design space for full integration of active and passive devices of a low-swing buck converter on the same die, for a target CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 to 0.9 V with a low-swing dc-dc converter based on a 0.18-/spl mu/m CMOS technology. The power dissipation of a low-swing dc-dc converter is reduced by 27.9% as compared to a standard full-swing dc-dc converter. 相似文献
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Vankka J. Waltari M. Kosunen M. Halonen K.A.I. 《Solid-State Circuits, IEEE Journal of》1998,33(2):218-227
A direct digital synthesizer (DDS) with an on-chip D/A converter is designed and processed in a 0.8 μm BiCMOS. The on-chip D/A converter avoids delays and line loading caused by interchip connections. At the 150 MHz clock frequency, the spurious free dynamic range (SFDR) is better than 60 dBc at low synthesized frequencies, decreasing to 52 dBc worst case at high synthesized frequencies in the output frequency band (0-75 MHz). The DDS covers a bandwidth from DC to 75 MHz in steps of 0.0349 Hz with the frequency switching speed of 140 ns. The chip has a complexity of 19100 transistors with a die/core area of 12.2/3.9 mm2. The power dissipation is 0.6 W at 150 MHz at 5 V. The maximum operating clock frequency of the chip is 170 MHz 相似文献
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An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm2 in 0.5-μm standard digital CMOS technology 相似文献
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《Microwave Theory and Techniques》1983,31(1):2-10
The analog-to-digital converter (A/D) is a critical component of a signal processing system. GHz-rate A/D's will be required in many future systems. While Si bipolar based A/D's can easily meet 4-6-bit resolution requirements, excessive power dissipation (1 W per bit) limits their operation to 100-400-MHz sampling rates. Recently, GaAs MES-FET's have demonstrated high frequency operation with relatively low power dissipation. This paper describes the design of 2- and 3-bit A/D's using GaAs MESFET's. Monolithic integrated A/D circuits were fabricated and successfully operated at gigahertz sampling rates. This sampling rate is the highest reported for any AD technology at room temperature. The power dissipation is 150-200 mW per bit. With further improvements in comparator sensitivity, the design can be extended to 4-bit A/D for GHz rate operation. 相似文献
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Current-Fed Resonant Full-Bridge Boost DC/AC/DC Converter 总被引:1,自引:0,他引:1
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A 12-bit 1 Msample/s 25 mW analog-to-digital converter was designed. Linearity, offset, and gain errors of less than 1/2 LSB have been achieved using an EEPROM memory trimming scheme. The EEPROM memory array, programmed during testing, continuously drives a correction digital-to-analog converter (DAC) with code dependent correction factors. The analog-to-digital converter (ADC) uses a time-interleaved multistep architecture consisting of two banks of comparator arrays sharing a common reference ladder and EEPROM correction memory. A static EEPROM memory array optimizes the power dissipation, conversion rate, inter-stage gain errors, and charge injection. The resulting converter achieves high speed operation with minimal power dissipation 相似文献
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《Electron Devices, IEEE Transactions on》1983,30(1):2-10
the analog-to-digital converter (A/D) is a critical component of a signal processing system. GHz-rate A/D's will be required in many future systems. While Si bipolar based A/D's can easily meet 4-6-bit resolution requirements, excessive power dissipation (1 W per bit) limits their operation to 100-400-MHz sampling rates. Recently, GaAs MESFET's have demonstrated high frequency operation with relatively low power dissipation. This paper describes the design of 2- and 3-bit A/D's using GaAs MESFET's. Monolithic integrated A/D circuits were fabricated and successfully operated at gigahertz sampling rates. This sampling rate is the highest reported for any A/D technology at room temperature. The power dissipation is 150-200 mW per bit. With further improvements in comparator sensitivity, the design can be extended to 4-bit A/D for GHz rate operation. 相似文献
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Yamagishi A. Ishikawa M. Tsukahara T. Date S. 《Solid-State Circuits, IEEE Journal of》1998,33(2):210-217
A 2 GHz direct digital frequency synthesizer (DDFS) chip-set is presented which operates at a very low supply voltage of 2 V. The chip-set consists of a CMOS DDFS LSI which synthesizes a sine wave at 55 Msps with an internal 10 b digital-to-analog converter (DAC) and Si bipolar image-reject up-converters. To achieve both high purity and low power dissipation, we developed a distortion-free up-conversion architecture and an efficient ROM output bit-width reduction technique. Operation of 2 V for the entire chip-set becomes possible because of the use of both multithreshold-voltage CMOS in the D/A converters and current-folded double-balanced mixers in the microwave up-converters. The synthesizer achieves a wide spurious-free dynamic range of 50 dB and a low power dissipation of less than 160 mW at 2 GHz 相似文献