载波跟踪环路鉴别器的改进设计及FPGA实现

目前GPS接收机载波跟踪环路往往采用易于硬件实现,但精度不高、跟踪速度慢的鉴别器。针对该现状,在现有CORDIC算法基础上加以改进,并在FPGA上完成了二象限反正切鉴相器和四象限反正切鉴频器的设计。在原有CORDIC算法上加入象限转换和相位转换功能,使反正切计算范围扩大至-180°~180°;通过增加鉴频器门限设定,消除了导航电文翻转带来的误差。该设计方案使载波跟踪鉴别器共用一个反正切模块,减少了硬件资源。最终仿真结果表明：改进后的鉴别器提高了鉴相与鉴频的精度,加快了稳定跟踪的速度。     

雷达目标角度跟踪环路滤波器设计新方法

角度跟踪环路在机载雷达对目标的距离、速度、角度3维联合跟踪中起着至关重要的作用。该文分析指出传统采用卡尔曼滤波算法形成角度跟踪环路对机动目标角度进行跟踪时跟踪精度低,角跟踪误差收敛速度慢的缺点,提出弯曲度检测跟踪环路滤波器(Bend Degree Tracking Loop Filter, BDTLF)设计方法,其利用弯曲度检测角度曲线拐点,自适应地调节环路滤波器环路等效噪声带宽,并以此来控制角度跟踪环路。此算法加快了角跟踪误差的收敛速度,减轻了拐点处的角度滤波扰动,保持了滤波性能的连续性。计算机仿真结果验证了该文方法相比于卡尔曼滤波算法、粒子滤波算法、-- 滤波算法及恒定系数环路滤波器方法,对弱机动目标角度跟踪具有更加出色的性能。     

一种低复杂度GPS载波跟踪环路设计

 GPS接收机载波跟踪环路的鉴别器和滤波器设计决定了跟踪环路的性能,也在很大程度上决定了GPS接收机的性能.本文在分析了传统锁相环和锁频环鉴别器算法的基础上,提出了一种锁相锁频环共用四象限反正切函数单元的鉴别器算法;同时,在研究了基于双线性Z变换积分器与矩形波数字积分器的滤波算法基础上,提出了一种基于矩形波数字积分器的锁频环辅助锁相环的滤波器算法.综合这两种新算法给出一种低复杂度的GPS接收机锁相锁频环设计方法.通过理论分析与仿真实验,证实该GPS载波跟踪环路设计不但具有良好的跟踪性能,且与传统设计方案相比具有运算量小,复杂度低,占用资源少等优点,更易于工程实现.     

基于FRFT的多普勒频率跟踪算法

高动态环境下卫星通信终端面临高动态和低信噪比问题,传统载波跟踪方法难以在高动态应力和跟踪精度两方面取得较好折中,在信号设计中考虑插入分散导频用于跟踪载波,可在低信噪比下实现高机动用户多普勒频移捕获及多普勒频率变化率的跟踪。给出了一种基于FRFT的频率变化率估计方法,利用估计值辅助载波跟踪环路。理论分析与计算机仿真表明,在典型高动态参数条件下,基于分散导频的多普勒频率跟踪算法和传统载波跟踪方法相比,灵敏度提高2 dB以上,Es/N0工作点可低至0 dB以下,跟踪范围可达符号速率的2倍,频率跟踪的均方根误差小于符号速率的1%,性能损失小于0.1 dB。     

一种复合伪随机码跟踪环路设计及误差分析

该文针对当存在较大的载波相位跟踪误差时可能导致传统的复合码相干型跟踪环路失效的问题提出一种复合码非相干型跟踪环路。通过给出基于二进制偏移载波(BOC)调制的复合码的构造和相关特性分析,设计了具有非相干型鉴别器的跟踪环路,并分析了环路的跟踪误差。分析和仿真结果表明该环路解决了在存在较大载波相位误差时跟踪环路失效的问题,且具有良好的跟踪性能。     

EBPSK载波同步中的相位误差分析

载波同步是通信中的重要环节。该文分析了EBPSK载波同步中的相位误差。首先在包含窄带高斯噪声的条件下,通过建立锁相环线性化模型,推导了EBPSK载波恢复中的输出相位噪声方差;其次在相同的参数条件下,与BPSK的平方环和Costas环输出相位噪声方差进行对比,给出了不同输入信噪比和环路带宽下的仿真结果。研究表明,在EBPSK占空比1:9,相位跳变/4,输入信噪比小于6 dB时,恢复出的载波要比BPSK更加精确。     

GNSS接收机锁相环最佳环路带宽的选取

锁相环环路带宽值的选取对于锁相环的跟踪误差性能有重要影响。基于全球卫星导航系统(GNSS）接收机中常用锁相环结构与数学模型,首先介绍了锁相环及其重要组成部分环路滤波器的结构和原理,然后分析了环路带宽的取值对锁相环两个最重要的误差源——环路热噪声误差和晶振阿伦偏差的影响,给出了低动态下使锁相环总的跟踪误差最小的最佳环路带宽的理论表达式。对基于由现场可编程门阵列（FPGA）芯片、温补晶振和模/数接口电路构建的实际硬件接收机平台进行了验证,结果表明：当根据最佳环路带宽的理论表达式取环路带宽值时,锁相环的跟踪误差最小。所推得的理论表达式不仅可以应用于GNSS接收机,也适用于一般的载波跟踪环设计。     

加性白噪声下基带延迟锁定环跟踪精度的计算

研究了加性白噪声下基带延迟锁定环跟踪精度的计算问题,着重讨论了积分时间和环路带宽的关系.以码延迟相关鉴别器的等效鉴相模型为基础,研究了相关器输出噪声特性及其在输入端等效噪声的特性,推导了线性跟踪环输出噪声方差的计算公式,并得到了积分时间和环路带宽分别起主导作用时的简化计算公式,使两种不同的结论得到了统一.     

极低载噪比高动态信号的载波跟踪锁频环研究

为提高极低载噪比下锁频环对含较大多普勒变化率成份的高动态回波信号的频率跟踪能力,提出了一种改进的锁频环结构,在传统锁频环基础上,增加1个环专门用于跟踪回波信号的多普勒变化率.鉴别器采用2种频率估计算法相互配合获得了宽鉴频范围和高鉴别精度,对鉴别结果采用野值剔除技术,保证了极低载噪比条件下环路的工作稳定,环路滤波器采用多级带宽逐级切换策略,兼顾了频率跟踪精度和环路收敛速度,仿真结果表明:改进锁频环能对载噪比低至16 dBHz的高动态回波信号进行稳定可靠、高精度的频率跟踪.     

一种大频偏和低信噪比条件下的全数字锁相环设计

全数字锁相环设计是相干解调全数字接收机载波同步和位同步的关键技术,而大频偏和低信噪比分别从两个方面增加了环路设计的难度.该文在此背景下,以捕获时间和跟踪性能为指标,从模拟环路分析出发,给出一种适用于大频偏和低信噪比条件的全数字锁相环设计.     

An adaptive PLL tuning system architecture combining high spectralpurity and fast settling time

An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer-N PLLs): a signal-to-noise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB     

电反馈对FM光发射机信噪比性能的改善

本文研究了电反馈半导体激光器作为FM光发射机的信噪比性能。分析表明:电反馈可以改善FM光发射机的信噪比性能。这种改善在适当的反馈条件下可达近30dB。反馈环路存在着最佳增益使信噪比达到最大。     

次谐波调制下光注入DFB-LD结构的可调谐光电振荡器

为实现具有高频谱纯度、低相位噪声的宽带可调谐微波信号生成,提出并通过实验验证了一种次谐波信号调制下光注入半导体激光器结构的光电振荡器,其原理为通过利用光注入半导体激光器的单周期（P1）振荡工作状态和波长选择放大特性实现可调微波信号生成,并进一步通过在光电振荡环路中引入次谐波信号调制对系统生成微波信号的频率稳定性、边模抑制比与频谱纯度进行优化。实验结果表明,文中方案提出的光电振荡器可以生成输出功率大于5 dBm,频率调谐范围为12~18 GHz的微波信号。同时,系统生成的微波信号的3 dB带宽为100 kHz,边模抑制比可达 51 dB,且信号在频偏量为100 Hz和10 kHz处的相位噪声分别为?78 dBc/Hz和?109 dBc/Hz。此外,光电振荡器生成微波信号的频率调谐范围只受系统中使用的各类光电器件工作带宽的限制,通过采用具有更大带宽的光电器件可以实现更高频率的微波信号生成。     

Circuit design and performance analysis of carrier recovery loopfor digital DBS system in the presence of phase noise

The theoretical analysis of a digital satellite broadcasting system in the presence of phase noise is performed. An effective technique to design the carrier recovery circuit is also presented based on the analyzed loop parameters, such as degradation loss due to phase noise, average time to cycle slip, and carrier signal acquisition time. It is possible to design a system providing the optimal service and satisfying service requirements for a digital satellite broadcasting system. In this paper, the carrier recovery loop that provides optimal performance in the presence of phase noise exhibits the parameters of 0.707 for damping factor and 40 kHz for noise bandwidth. The designed phase-locked loop indicates a performance of 0.26 dB for impairment due to phase noise at 10^-3 BER, 3.88×10⁶ hours for average time to cycle slip, and 34 msec for carrier signal acquisition time. The carrier acquisition time of the designed carrier recovery circuit is in accordance with the analyzed result     

Partially coherent DS-SS performance in frequency selectivemultipath fading

The bit-error rate (BER) performance of a direct sequence spread spectrum (DS-SS) signal, operating over a multipath Rayleigh fading channel, is investigated when corrupted by phase noise as well as additive white Gaussian noise (AWGN). The phase noise arises from phase locked loop (PLL) dynamics and results in imperfect receiver phase estimates whereby the phase errors assume Tikhonov densities. The phase estimates are used by a multipath-combining RAKE receiver for demodulation. Approximate upper-bounds on the bit error probability are obtained and evaluated for different combinations of channel parameters and for various values of the average loop signal-to-noise ratio (SNR). Results indicate that for a PLL with loop SNR 10 dB above the system E _b/η₀, the degradation is less than 3 dB, and for a loop SNR of 20 dB above E_b/η₀, the degradation is less than 1 dB     

GPS接收机载波跟踪环设计与分析

针对GPS接收机载波跟踪环环宽与跟踪的动态性能问题,在分析影响GPS信号动态性能的主要参数热噪声、晶振Allan相位噪声、晶振振动相位噪声和动态应力的基础上,通过对不同阶数的锁相环、锁频环跟踪门限分析与仿真,主要解决了如何设计GPS接收机的载波跟踪环路的带宽,并使系统性能达到最佳的问题,即使用环宽为18 Hz的二阶锁相环辅助环宽为10 Hz的三阶锁频环可以跟踪动态范围小于10 g、100 g/s的高动态信号。     

Fully Differential 5‐GHz LC‐Tank VCOs with Improved Phase Noise and Wide Tuning Range

In this paper, we propose two LC voltage‐controlled oscillators (VCOs) that improve both phase noise and tuning range. With both 1/f induced low‐frequency noise and low‐frequency thermal noise around DC or around harmonics suppressed significantly by the employment of a current‐current negative feedback (CCNF) loop, the phase noise in the CCNF LC VCO has been improved by about 10 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise of the CCNF VCO was measured as ?112 dBc/Hz at 6 MHz offset from 5.5 GHz carrier frequency. Also, we present a bandwidth‐enhanced LC VCO whose tuning range has been increased about 250 % by connecting the varactor to the bases of the cross‐coupled pair. The phase noise of the bandwidth‐enhanced LC‐tank VCO has been improved by about 6 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise reduction has been achieved because the DC‐decoupling capacitor Cc prevents the output common‐mode level from modulating the varactor bias point, and the signal power increases in the LC‐tank resonator. The bandwidth‐enhanced LC VCO represents a 12 % bandwidth and phase noise of ?108 dBc/Hz at 6 MHz offset.     

PLL FM demodulator performance under Gaussian modulation

A widespread test of the phase-locked loop (PLL) FM demodulator under Gaussian modulation is simulated using the Monte Carlo method. Unified noise-free and noise performance analyses of the PLL FM demodulator are presented. Substantial reduction of the modulation limit by the input bandpass filter is reported in the region of the input bandwidth of practical interest. Bessel bandpass filters of order greater than two are shown to compare favorably with Butterworth filters in front of the PLL FM demodulator relative to the intermodulation (IM) distortion. A lower bound on the loop noise bandwidth is found by minimizing the output click rate for given IM distortion specifications. FM threshold of 4 and 7 dB for the root-mean-square (RMS) frequency deviation-to-message bandwidth ratio 0.1 and 1.0, respectively, is reported on the worst-case IM distortion of 45 dB     

一种降低高频噪声的前置全差分运算放大器

提出了一种降低高频噪声的前置全差分放大器.运放内部采用了两组偏置电路,一组用于单位增益缓冲器电路,一组用于放大电路.为了确保电路稳定性又不增加设计难度,将单位增益缓冲器电路与共模反馈回路结合起来.设计采用HHNEC 0.18μm BCD工艺,Cadence Spectre仿真表明,正常工作时共模反馈的环路增益84.93dB,单位增益带宽9.52MHz,相位裕度67.62°;启动时单位增益缓冲器电路的环路增益85.18dB,单位增益带宽8.93MHz,相位裕度67.2°;关断时,单位增益缓冲器电路的环路增益63.26dB,单位增益带宽2.28MHz,相位裕度88.66°.实测表明,设计降低了D类音频功放在开启和关断时的噪声.