3-D Integration of 10-GHz Filter and CMOS Receiver Front-End

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mum CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.     

165-GHz Transceiver in SiGe Technology

Two D-band transceivers, with and without amplifiers and static frequency divider, transmitting simultaneously in the 80-GHz and 160-GHz bands, are fabricated in SiGe HBT technology. The transceivers feature an 80-GHz quadrature Colpitts oscillator with differential outputs at 160 GHz, a double-balanced Gilbert-cell mixer, 170-GHz amplifiers and broadband 70-GHz to 180-GHz vertically stacked transformers for single-ended to differential conversion. For the transceiver with amplifiers and static frequency divider, which marks the highest level of integration above 100 GHz in silicon, the peak differential down-conversion gain is -3 dB for RF inputs at 165 GHz. The single-ended, 165-GHz transmitter output generates -3.5 dBm, while the 82.5-GHz differential output power is +2.5 dBm. This transceiver occupies 840 mum times 1365 mum, is biased from 3.3 V, and consumes 0.9 W. Two stand-alone 5-stage amplifiers, centered at 140 GHz and 170 GHz, were also fabricated showing 17 dB and 15 dB gain at 140 GHz and 170 GHz, respectively. The saturated output power of the amplifiers is +1 dBm at 130 GHz and 0 dBm at 165 GHz. All circuits were characterized over temperature up to 125degC. These results demonstrate for the first time the feasibility of SiGe BiCMOS technology for circuits in the 100-180-GHz range.     

A 2.45-GHz Near-Field RFID System With Passive On-Chip Antenna Tags

The design of a 2.45-GHz near-field RF identification (RFID) system with passive on-chip antenna (OCA) tags is very challenging as the efficiency of RF power conversion is very low. It poses multidisciplinary research challenges such as ultra-low-power circuits design, semiconductor process technology, and integrated antenna design. This paper describes the designs of such an RFID system, the reader, and OCAs, as well as the passive tag integrated circuits in detail. The passive tag chip with 128-bit nonvolatile memory has been realized using CMOS 0.13- technology. The OCA is fabricated on top of the chip using post-processing technology. The complete RFID tag with an integrated OCA is smaller than 0.5- with a thickness of 0.1 mm. With the reader generating an output power of 0.5 W, the RFID system is able to perform with RF read/write functions at a distance of .     

A 23.8-GHz SOI CMOS tuned amplifier

A 23.8-GHz tuned amplifier is demonstrated in a partially scaled 0.1-μm silicon-on-insulator CMOS technology. The fully integrated three-stage amplifier employs a common-gate, source-follower, and cascode with on-chip spiral inductors and MOS capacitors. The gain is 7.3 dB, while input and output reflection coefficients are -45 and -9.4 dB, respectively. Positive gain is exhibited beyond 26 GHz. The amplifier draws 53 mA from a 1.5-V supply. The measured on-wafer noise figure is 10 dB, while the input-referred third-order intercept point is -7.8 dBm. The results demonstrate that 0.1-μm CMOS technology may be used for 20-GHz RF applications and suggest even higher operating frequencies and better performance for further scaled technologies     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz fT silicon bipolar technology

Clock and data recovery (CDR) circuits are key electronic components in future optical broadband communication systems. In this paper, we present a 40-Gb/s integrated CDR circuit applying a phase-locked loop technique. The IC has been fabricated in a 50-GHz f _T self-aligned double-polysilicon bipolar technology using only production-like process steps. The achieved data rate is a record value for silicon and comparable with the best results for this type of circuit realized in SiGe and III-V technologies     

A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems

A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure and -112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.     

A 2-GHz, 6-mW BiCMOS frequency synthesizer

A 128-channel pulse-swallow frequency synthesizer includes a 3-mW VCO, a 2.2-mW 16/17 dual-modulus prescaler, a 9-b program counter, and a 7-b swallow counter. The circuit is fully integrated with the exception of the loop-filter capacitor. The ECL prescaler incorporates current sharing and circuit stacking techniques to reduce power consumption. Fabricated in a 1-μm, 20-GHz BiCMOS process, the circuit operates from a 3-V supply and occupies an active area of 0.28 mm²     

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

As CMOS processes advanced, the integration of radio-frequency (RF) integrated circuits was increasing. In order to protect the fully-integrated RF transceiver from electrostatic discharge (ESD) damage, the transmit/receive (T/R) switch of transceiver frond-end should be carefully designed to bypass the ESD current. This work presented a technique of embedded ESD protection device to enhance the ESD capability of T/R switch. The embedded ESD protection devices of diodes and silicon-controlled rectifier (SCR) are generated between the transistors in T/R switch without using additional ESD protection device. The design procedure of RF circuits without ESD protection device can be simplified. The test circuits of 2.4-GHz transceiver frond-end with T/R switch, PA, and LNA have been integrated and implemented in nanoscale CMOS process to test their performances during RF operations and ESD stresses. The test results confirm that the embedded ESD protection devices can provide sufficient ESD protection capability and it is free from degrading circuit performances.     

Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode

The designs of two fully integrated CMOS cascode distributed amplifiers (DAs) with 14-GHz and 22-GHz bandwidth are presented. Cascode gain cells and m-derived matching sections are used to enhance the gain and bandwidth performance. These amplifiers demonstrated the highest frequency and widest bandwidth of operation for amplifiers using regular CMOS processes to date. This paper also describes the analysis to design the cascode CMOS DA, together with the small-signal models, EM simulation of the spiral inductors on the silicon substrate, and the analysis of the cascode device. Good agreement between measured and simulated results was achieved for both of the DA designs.     

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

A fully integrated 5-GHz low-power ESD-protected low-noise amplifier (LNA), designed and fabricated in a 90-nm RF CMOS technology, is presented. This 9.7-mW LNA features a 13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB. An on-chip inductor, added as "plug-and-play," i.e., without altering the original LNA design, is used as ESD protection for the RF pins to achieve sufficient ESD protection. The LNA has an ESD protection level up to 1.4 A transmission line pulse (TLP) current, corresponding to 2-kV Human Body Model (HBM) stress. Experimental results show that only minor RF performance degradation is observed by adding the inductor as a bi-directional ESD protection device to the reference LNA.     

SiGe differential transimpedance amplifier with 50-GHz bandwidth

InP and SiGe technologies are both attractive for design of circuits operating at 40 GB/s and beyond. In this paper, we describe a fully differential SiGe transimpedance amplifier (TIA) suitable for differential phase-shift keying applications. The TIA exhibits 49 dB-/spl Omega/ transimpedance, greater than 50-GHz bandwidth, and input-referred current noise less than 30 pA//spl radic/Hz. For comparison, we have also developed a similar TIA in an InP double-heterostructure bipolar transistor technology. The InP TIA had 48 dB-/spl Omega/ transimpedance and 49-GHz bandwidth.     

Development of 60-GHz front-end circuits for a high-data-rate communication system

Recent results from a Swedish program for development of 60-GHz monolithic microwave integrated circuits (MMICs) for high-data-rate communication links are presented. Front-end circuits such as mixers, amplifiers, frequency multipliers, IF amplifiers with gain control, and voltage-controlled oscillators (VCOs) have been realized utilizing GaAs PHEMT and MHEMT technologies. A newly developed 7.5-GHz coupled Colpitt VCO shows a minimum phase noise of -95 dBc at 100 kHz offset. A second-harmonic 14-GHz VCO shows a minimum phase noise of less than -90 dBc at 100 kHz. A novel balanced 7-28-GHz MMIC frequency quadrupler is described and compared with a single-ended quadrupler at the same input frequencies. To demonstrate its feasibility and potential application, the quadrupler is combined with the Colpitt VCO and the output characteristics of the resulting 30-GHz MMIC source are measured. A three-stage MHEMT wide-band amplifier covering 43-64 GHz with a gain of 24 dB, a minimum noise figure of 2.5 dB, and a passband ripple of 2 dB is also described. In future 60-GHz systems for mass markets where cost is of utmost importance, Si-based technologies, especially CMOS, are highly interesting. Some recent circuit results based on a 90-nm CMOS technology are also reported.     

Chip-package codesign of a low-power 5-GHz RF front end

Future high-performance wireless communication applications such as wireless local area networks (WLANs) around 5 GHz require low-power and highly integrated transceiver solutions. The integration of the RF front end especially poses a great challenge in these applications, as traditional front-end implementations require a large number of external passive components. In this paper, we present the single-package integration of complete transceivers based on a thin-film multichip module (MCM) technology with integrated passives. The MCM substrate is a a common carrier onto which different ICs are mounted. passive components such as RF bandpass filters, inductors, capacitors, and resistors are directly integrated into the MCM substrate with the use of the multilayer structure of the MCM technology. The “system-on-a-package” approach is illustrated with a voltage-controlled oscillator for Digital European Cordless Telephone (DECT) applications and a 5-GHz WLAN front end. These examples indicate that this approach yields a compact low-power implementation of complete transceivers for high-performance wireless applications     

A 12-GHz silicon bipolar dual-conversion receiver for digital satellite applications

A 12-GHz monolithic silicon bipolar receiver for digital video broadcasting via satellite (DVB-S) is presented. The receiver is based on a dual-conversion superheterodyne architecture that employs a single LO integrated in the same die. To comply with the stringent LO phase noise requirement of -101 dBc/Hz at 100 kHz offset from the carrier, an innovative VCO topology, based on a three-layer monolithic transformer, was used. The VCO exhibits a phase noise of -102 dBc/Hz at 100 kHz offset from a 5.3-GHz carrier and a 1.1-GHz tuning range. At 12 GHz, the conversion gain is 33.6 dB, the single-sideband noise figure is 5.9 dB and the output IP3 is +16 dBm. This work reports the first 12-GHz DVB-S monolithic receiver integrated in a low-cost silicon bipolar technology.     

24-GHz Frequency-Modulation Continuous-Wave Radar Front-End System-on-Substrate

Design and implementation of a 24-GHz frequency-modulation continuous-wave radar front-end system is presented and discussed, and its hybrid planar and waveguide building blocks are fully integrated on one single substrate. A flexible and compact integration methodology on the basis of the substrate-integrated-circuits concept is deployed to design such a microwave front-end system-on-substrate. In this study, it is found that this surface-volume hybrid integration scheme not only enables the complete system integration of planar and nonplanar microwave circuits, but also combines respective advantages of such structures in connection with microstrip lines (planar) and waveguides (nonplanar). Design strategies of the system building blocks including mixers, power dividers, and antenna arrays are discussed together along with the measured results. To verify the developed radar prototype, laboratory-based target-range measurements are conducted.     

A 2.4-GHz 24-dBm SOI CMOS Power Amplifier With Fully Integrated Reconfigurable Output Matching Network

In this paper, the potential of load adaptation for enhanced backoff efficiency in RF power amplifiers (PAs) has been investigated through a 0.13-mum silicon-on-insulator (SOI) CMOS fabrication technology. The RF power performance of the adopted SOI CMOS process has been preliminarily characterized by on-wafer load-pull measurements on a custom unit power transistor. A 2.4-GHz 24-dBm 2-V SOI CMOS PA with fully integrated reconfigurable output matching network has then been designed and experimentally characterized. A significant efficiency improvement of up to 34% has been achieved through load adaptation, peak efficiency being as high as 65%. Linear operation has also been demonstrated under two-tone excitation, as a 16-dBm output power has been attained while complying with a - 40-dBc third-order intermodulation distortion specification.     

Fully integrated 2.2-mW CMOS front end for a 900-MHz wirelessreceiver

Low power consumption is the most important concern for integrated wireless devices. This paper illustrates low-power design principles in the CMOS context. They entail seeking strategic combinations of high-quality off-chip passives with RF integrated circuits and searching for better architectures in wireless receivers to low power. The principles are illustrated with a fully integrated 2.2-mW 1.2-V front end for 900-MHz receiver, fabricated in 0.35-μm CMOS     

A production ready, 6-18-GHz, 5-b phase shifter with integratedCMOS compatible digital interface circuitry

A producible, high-yield, monolithic 6-18-GHz, 5-b phase shifter with integrated standard CMOS compatible digital interface circuitry has been developed for use over the -55 to +90°C temperature range. Differential phase shift is achieved using high-pass and low-pass filter structures. The integrated digital interface circuitry produces complementary outputs that are used to bias the phase-shifter bits. The integration of the digital interface circuitry, made with microwave FETs, reduced the phase-shifter bit control bias lines by a factor of 2. The phase shifter was fabricated at both Raytheon's and Texas Instruments' GaAs foundries in production quantities using a standard microwave process. Complete on-wafer RF tests were performed to screen the phase-shifter circuits and determine electrical yield. The phase shifter has an r.m.s. phase error <10° from 6.5 to 18 GHz, maximum insertion loss of 14 dB, and an r.m.s. amplitude error <0.8 dB over the 6-18-GHz band