A pipelined temporal difference imager

A 189/spl times/182 active pixel sensor (APS) for temporal difference computation is presented. The temporal difference imager (TDI), fabricated in 0.5-/spl mu/m CMOS process, contains in-pixel storage elements for a previous image frame. Difference double-sampling circuits are used to suppress the fixed pattern noise in both images and to compute the difference between the corrected images. The pixel area occupies 25 /spl mu/m by 25 /spl mu/m (using 0.7-/spl mu/m scalable rules), with fill factor of 30%. A novel pipelined readout technique is described, which is used to improve the accuracy of the temporal difference computation. With this pipelined readout architecture, >8-bit precision for the difference image and low spatial droop across the difference image is achieved. The chip consumes 30 mW at 50 fps from a 5-V power supply.     

Output stage based high-resolution min/max and rank-order filters

A general architecture for analog implementation of min/max, median, and other rank-order filters is presented. The circuit settles in a single iteration and exhibits low error, even for closely spaced input values or large number of inputs. Increased gain in the global feedback mechanism avoids the large corner error typical of conventional (voltage-follower based) analog winner-take-all and other rank-order filters. The architecture comprises a parallel combination of two-stage amplifiers with common output, where the choice of output stage determines the type of computation performed by the circuit; a common-source with active load generates a min/max filter, while a CMOS inverting amplifier yields a median (or other rank-order) filter. Experimental results are included from a nine-element 45 /spl mu/m /spl times/ 358 /spl mu/m prototype fabricated in 1.6 /spl mu/m CMOS technology.     

A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

General-purpose 128/spl times/128 SIMD processor array with integrated image sensor

A CMOS image sensor/processor chip fabricated in a 0.35 /spl mu/m CMOS technology is presented. The chip contains a general purpose software-programmable SIMD array of 128/spl times/128 processing elements. It executes over 20 GOPS while dissipating 240 mW of power and achieves pixel-processor density of 410 cells/mm/sup 2/. Performance and accuracy measurement results are given.     

CMOS image sensor with mixed-signal processor array

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.     

A 4 /spl mu/m NMOS NAND structure PLA

A PLA of NAND structure, using a NMOS Si gate process, has been developed to minimize chip area and maintain medium fast speed. The smallest memory cell size of 7/spl times/9 /spl mu/m is achieved by using ion implantation for PLA bit programming with 4 /spl mu/m design rules. Dynamic clocking scheme and self-timing circuits which are used in this PLA are described. With PLA size at 20/spl times/20/spl times/20, transistor size of 8 /spl mu/m/4 /spl mu/m, and cell size of 7/spl times/12 /spl mu/m, an internal access time of 150 ns is achieved with an external 4 MHz clock. Measured circuit power dissipation is 20 mW under normal conditions.     

A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply

A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98 dB with 2 dB gain steps and is controlled by 6-bit gain control bits for a 3 V power supply. It has been fabricated in a 0.5 /spl mu/m 15 GHz f/sub T/ Si BiCMOS process and draws 13 mA. The active die area taken up by the circuit is 400 /spl mu/m /spl times/ 1170 /spl mu/m. A noise figure (NF) of 4.9 dB was measured at the maximum gain setting. In addition, an analysis of the bias current generation to provide dB-linear gain control is presented.     

A subnanosecond integrated switching circuit with MESFET's for LSI

Using a simple channel implantation step, the choice of the threshold voltage determines speed and power. Illustrations are given by the example of a 3-input NOR-gate with 1/spl times/5-/spl mu/m/SUP 2/ channel geometry for the switching transistors. A design with dual threshold voltages allowing the optimization of power consumption while keeping subnanosecond propagation delay times is presented and applied to a speed- and power-optimized dual-type MESFET NOR-gate. Examples are presented of experimental d.c. characteristics measured on fabricated samples exhibiting an average power consumption of 150 /spl mu/W. A propagation delay time of 0.8 ns is deduced for a fan-out of 3. This performance is discussed in conjunction with a set of parameters including geometry, technological reproducibility, and circuit design requirements. It appears that geometries of about 1 /spl mu/m lead to the best compromise for fast switching and optimized LSI organization.     

A miniaturized Wilkinson power divider with CMOS active inductors

A miniaturized Wilkinson power divider implemented in a standard 0.18-/spl mu/m CMOS process is presented in this letter. By using active inductors for the circuit implementation, a significant area reduction can be achieved due to the absence of distributed components and spiral inductors. The power divider is designed at a center frequency of 4.5GHz for equal power dividing with all ports matched to 50/spl Omega/. Drawing a dc current of 9.3mA from a 1.8-V supply voltage, the fabricated circuit exhibits an insertion loss less than 0.16dB and a return loss better than 30dB at the center frequency while maintaining good isolation between the output ports. The active area of the miniaturized Wilkinson power divider is 150/spl times/100/spl mu/m/sup 2/, which is suitable for system integration in monolithic microwave integrated circuit (MMIC) applications.     

A 16-Mb MRAM featuring bootstrapped write drivers

A 16-Mb magnetic random access memory (MRAM) is demonstrated in 0.18-/spl mu/m three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42/spl mu/m/sup 2/ 1-transistor 1-magnetic tunnel junction (1T1MTJ) cell, measures 79 mm/sup 2/ and features a /spl times/16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented.     

A 2.0-/spl mu/m pixel pitch MOS image sensor with 1.5 transistor/pixel and an amorphous Si color filter

In this paper, an ultrafine pixel size (2.0/spl times/2.0 /spl mu/m/sup 2/) MOS image sensor with very high sensitivity is developed. The key technologies that realize the MOS image sensor are a newly developed pixel circuit configuration (1.5 transistor/pixel), a fine 0.15-/spl mu/m design rule, and an amorphous Si color filter (Si-CF). In the new pixel circuit configuration, a unit pixel consists of one photodiode, one transfer transistor, and an amplifier circuit with two transistors that are shared by four neighboring pixels. Thus, the unit pixel has only 1.5 transistors. The fine design rule of 0.15 /spl mu/m enables reduction of wiring area by 40%. As a result, a high aperture ratio of 30% is achieved. A newly developed Si-CF realizes the 1/10 thickness of that of the conventional organic-pigment CF, giving rise to high light-collection efficiency. With these three technologies combined, a high sensitivity of 3400 electrons/lx/spl middot/s is achieved even with a pixel size of 2.0/spl times/2.0 /spl mu/m/sup 2/.     

A low power resistive load 64 kbit CMOS RAM

A fully asynchronous 8K word/spl times/8 bit CMOS static RAM with high resistive load cells is described. For fabricating the RAM, an advanced double polysilicon 2 /spl mu/m CMOS technology has been developed. Internally clocked dynamic peripheral circuits with address transition detectors are implemented to achieve high speed and low power simultaneously. A new CMOS fault-tolerant circuit technology is also introduced for improving fabrication yield without sacrificing operating speed or standby power. The resulting cell size and die size are 15/spl times/19 /spl mu/m and 4.87/spl times/7.22 mm, respectively. The RAM offers, typically, 70 ns access time, 15 mW operating power, and 10 /spl mu/W standby power.     

A low-power analog motion estimation processor for digital video coding

Analog circuit techniques can be beneficially applied to reduce the circuit complexity and power consumption of motion estimation processors for digital video encoding. However, analog circuits are sensitive to mismatch which affects motion estimation. This paper presents the design of an analog motion estimation processor which overcomes these limitations. A novel architecture is described featuring pixel reuse and input offset error cancellation. The proof-of-concept realization was fabricated in 0.8-/spl mu/m CMOS, and operates on 4/spl times/4 pixel blocks and a search area of 8/spl times/8 pixels. However, the architecture is scalable to larger block sizes and more advanced technologies. Measured results for various QCIF video sequences at 15-f/s showed excellent PSNR performance. The prototype dissipates 0.9 mW of power from a single 3-V power supply and occupies an area of 0.95 mm/sup 2/. Energy consumption is 1.51 nJ per motion vector.     

A very low-complexity space-time block decoder (STBD) ASIC for wireless systems

This paper presents a computationally efficient application-specific integrated circuit (ASIC) implementation for the decoding of space-time block codes (STBCs) . Alternative methods of evaluating the originally proposed maximum-likelihood decision metrics are explored at the algorithm and architectural level. At the algorithm level, unique decoding techniques are developed that result in computation savings of as much as 65%. At the architectural level, a low-computation symmetrical approach for the implementation of the proposed algorithm is presented. The proposed ASIC architecture offers considerable computation reductions leading to substantial power and area savings compared to a direct implementation of the original algorithm. The proposed architecture was realized in an ASIC referred to as the ST block decoder ASIC. The chip was fabricated using 0.18-/spl mu/m CMOS technology and occupies a core area of 0.25 mm/sup 2/. The ASIC architecture is highly scalable and can implement 2 /spl times/ 2, 8 /spl times/ 3, and 8 /spl times/ 4 STBCs with modulation formats ranging from binary-phase shift keying (BPSK) to 16 quadrature amplitude modulation (QAM), and can operate at any symbol rate up to 20 Mbaud. Depending on the mode of operation, the decoder power consumption ranges from 0.54 mW for 2 /spl times/ 2 BPSK systems to 1.89 mW for 8 /spl times/ 4 16-QAM systems.     

A micropower centroiding vision processor

A biologically-inspired hybrid vision chip is presented for real-time object-based processing for tasks such as centroiding, sizing and counting of enclosed objects. This system presents the first silicon retina capable of centroiding and sizing multiple objects in true parallel fashion. Based on a novel distributed algorithm, this approach uses the input image to enclose a feedback loop to realize a data-driven pulsating action. The sensor provides a resolution of 48 /spl times/ 48 pixels with a 85 /spl mu/m/spl times/85 /spl mu/m pixel footprint and has been measured to consume 243 /spl mu/W at 1.8-V supply, achieving an equivalent computational efficiency of 724.64 MIPS/mW with a 500-/spl mu/s process time.     

On-chip timing measurement architecture with femtosecond resolution

A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200/spl times/185 /spl mu/m) in a 0.12 /spl mu/m CMOS process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.     

PWM digital pixel sensor based on asynchronous self-resetting scheme

In this letter, a pulse-width modulated digital pixel sensor is presented along with its inherent advantages such as low power consumption and wide operating range. The pixel, which comprises an analog processor and an 8-bit memory cell, operates in an asynchronous self-resetting mode. In contrast to most CMOS image sensors, in our approach, the photocurrent signal is encoded as a pulse-width signal, and converted to an 8-bit digital code using a Gray counter. The dynamic range of the pixel can be adapted by simply modulating the clock frequency of the counter. To test the operation of the proposed pixel architecture, an image sensor array has been designed and fabricated in a 0.35-/spl mu/m CMOS technology, where each pixel occupies an area of 45/spl times/45 /spl mu/m/sup 2/. Here, the operation of the sensor is demonstrated through experimental results.     

Piezoelectric micro-power generation interface circuits

New power conversion circuits to interface to a piezoelectric micro-power generator have been fabricated and tested. Circuit designs and measurement results are presented for a half-wave synchronous rectifier with voltage doubler, a full-wave synchronous rectifier and a passive full-wave rectifier circuit connected to the piezoelectric micro-power generator. The measured power efficiency of the synchronous rectifier and voltage doubler circuit fabricated in a 0.35-/spl mu/m CMOS process is 88% and the output power exceeds 2.5 /spl mu/W with a 100-k/spl Omega/, 100-nF load. The two full-wave rectifiers (passive and synchronous) were fabricated in a 0.25-/spl mu/m CMOS process. The measured peak power efficiency for the passive full-wave rectifier circuit is 66% with a 220-k/spl Omega/ load and supplies a peak output power of 16 /spl mu/W with a 68-k/spl Omega/ load. Although the active full-wave synchronous rectifier requires quiescent current for operation, it has a higher peak efficiency of 86% with an 82-k/spl Omega/ load, and also exhibits a higher peak power of 22 /spl mu/W with a 68-k/spl Omega/ load which is 37% higher than the passive full-wave rectifier.     

Two-13 ns-64K CMOS SRAM's with very low active power and improved asynchronous circuit techniques

64K/spl times/1 and 16K/spl times/4 CMOS SRAMs which achieve an access time of 13 ns and less than 12-mA active current at 10 MHz are described. A double-metal 1.5-/spl mu/m p-well process is used. A chip architecture with local amplification improves signal speed and data integrity. Address stability detection techniques are introduced as a method of assuring full asynchronicity over a wide range of conditions. A chip-select speed-up circuit allows high-speed access from a power-down mode. A memory cell design is presented which has improved layout efficiency (area of 189 /spl mu/m/SUP 2/), yet provides a very high cell ratio of 3:1 for signal stability and margin. Experimental results are presented which demonstrate full performance under address skews and other asynchronous input conditions. High-speed enable access and address access are observed over a wide range of operating conditions.     

Self-heating and trapping effects on the RF performance of GaN MESFETs

RF power performances of GaN MESFETs incorporating self-heating and trapping effects are reported. A physics-based large-signal model is used, which includes temperature dependences of transport and trapping parameters. Current collapse and dc-to-RF dispersion of output resistance and transconductance due to traps have been accounted for in the formulation. Calculated dc and pulsed I-V characteristics are in excellent agreement with the measured data. At 2 GHz, calculated maximum output power of a 0.3 /spl mu/m/spl times/100 /spl mu/m GaN MESFET is 22.8 dBm at the power gain of 6.1 dB and power-added efficiency of 28.5% are in excellent agreement with the corresponding measured values of 23 dBm, 5.8 dB, and 27.5%, respectively. Better thermal stability is observed for longer gate-length devices due to lower dissipation power density. At 2 GHz, gain compressions due to self-heating are 2.2, 1.9, and 0.75 dB for 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs, respectively. Significant increase in gain compression due to thermal effects is reported at elevated frequencies. At 2-GHz and 10-dBm output power, calculated third-order intermodulations (IM3s) of 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs are -61, -54, and - 45 dBc, respectively. For the same devices, the IM3 increases by 9, 6, and 3 dBc due to self-heating effects, respectively. Due to self-heating effects, the output referred third-order intercept point decreases by 4 dBm in a 0.30 /spl mu/m/spl times/100 /spl mu/m device.