MONOS memory in sequential laterally solidified low-temperature poly-Si TFTs

A metal-oxide-nitride-oxide-polysilicon (MONOS) memory device fabricated by sequential lateral solidified (SLS) low-temperature polycrystalline silicon (poly-Si) technology on a glass substrate was investigated. The Si protrusions at grain boundaries (GBs) as a result of the SLS process can be well controlled and located along the width direction of the transistor. Protrusions at the GBs are utilized as emitting source to achieve a MONOS memory device with low operation voltage (/spl les/ 20 V), fast program/erase time, and wide V/sub th/ window by field-enhanced channel hot electron injection for programming and field-enhanced band-to-band tunneling-induced hot hole injection for erase. This is the first study to demonstrate a nonvolatile memory device in low-temperature poly-Si thin-film transistor (LTPS TFT) technology, which can be integrated with TFT-liquid crystal display, to reduce power consumption for mobile applications.     

Field enhancement of omega-shaped-gated poly-Si TFT SONOS memory fabricated by a simple sidewall spacer formation

A novel omega-shaped-gated (Ω-Gate) poly-Si thin-film-transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices fabricated with a simple process have been proposed for the first time. The Ω-Gate structure inherently covered two sharp corners manufactured simply via a sidewall spacer formation. Due to the sharp corner geometry, the local electric fields across the tunneling oxide could be enhanced effectively, thus improving the memory performance. Based on this field enhanced scheme, the Ω-Gate TFT SONOS revealed excellent program/erase (P/E) efficiency and larger memory window as compared to the conventional planar (CP) counterparts. In addition, owing to the better gate controllability, the Ω-Gate TFT SONOS also exhibited superior transistor performance with a much higher on-current, smaller threshold voltage, and steeper subthreshold swing. Therefore, such an Ω-Gate TFT SONOS memory is very promising for the embedded flash on the system-on-panel applications.     

3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture

A three-dimensional (3D) stacked bit-line NAND flash memory is investigated. The fabrication process flow for the formation of a laterally-recessed bit-line stack is described. Program operation is simulated using a stacked bit-line structure. Inter-layer interference (ILI) is addressed and the minimum isolation oxide thickness between stacked bit-lines is extracted. Simple device and array with the laterally-recessed bit-line stack are fabricated and electrical characteristics are measured. A new array architecture having a connection gate is designed for the 3D stacked bit-line NAND flash memory application.     

Non-Volatile Memories for Removable Media

NAND Flash memory has become the preferred nonvolatile choice for portable consumer electronic devices. Features such as high density, low cost, and fast write times make NAND perfectly suited for media applications where large files of sequential data need to be loaded into the memory quickly and repeatedly. When compared to a hard disk drive, a limitation of the Flash memory is the finite number of erase/write cycles: most of commercially available NAND products are guaranteed to withstand 10$^{5}$ programming cycles at most. As a consequence, special care (remapping, bad block management algorithms, etc.) has to be taken when hard-drive based, read/write intensive applications, such as operating systems, are migrated to Flash-memory based devices. One of the basic requirements of the consumer market for data storage is the portability of stored data from one device to the other. Flash cards are the actual solution. A Flash card is a nonvolatile “system in package” in which a NAND Flash memory is embedded with a dedicated controller. This paper presents the basic features of the NAND Flash memory and the basic architecture of Flash cards. We provide an outlook on opportunities and challenges of future Flash systems.      

Poly-Si Thin-Film Transistor Nonvolatile Memory Using Ge Nanocrystals as a Charge Trapping Layer Deposited by the Low-Pressure Chemical Vapor Deposition

We have successfully developed and fabricated a poly-Si thin-film transistor (poly-Si TFT) nonvolatile memory using Ge nanocrystals (Ge-NCs) as a charge trapping layer. Process compatibility and memory operation of the device were investigated. The Ge-NC trapping layer was directly deposited by low-pressure chemical vapor deposition at 370 $^{circ}hbox{C}$. Results show that the new poly-Si TFT nonvolatile Ge-NC memory has good programming/erasing efficiency, long charge retention time, and good endurance characteristics. These results show that poly-Si TFT nonvolatile Ge-NC memory is the promising nonvolatile memory candidate for system-on-panel application in the future.      

Polysilicon thin-film transistors on polymer substrates

Different approaches to fabricate low-temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) on polymer substrates are reviewed and the two main routes are discussed: (1) standard fabrication of LTPS TFTs on glass substrates followed by a transfer process of the devices on the polymeric substrate; (2) direct fabrication of the devices on the polymeric substrate. Among the different techniques we have described in more detail the process we have recently developed for the fabrication of LTPS TFTs directly on ultra-thin polyimide (PI) substrate. LTPS TFT technology is particularly suited for high performance flexible electronics applications, due to the excellent device characteristics, good electrical stability and CMOS technology. Flexible display application remains the most attractive application for LTPS technology, especially for AMOLED displays, where device stability and the possibility to integrate the driving circuits make LTPS technology superior to all the other competitive TFT technologies. Among the other applications, particularly promising is also the application to flexible smart sensors, where integration of a front-end electronics is essential. Some examples of flexible gas sensors and pressure sensors, integrated with simple readout electronics based on LTPS TFTs and fabricated on ultra-thin PI substrate, are presented.     

Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application

A new stacked-nanowire device is proposed for 3-dimensional (3D) NAND flash memory application. Two single-crystalline Si nanowires are stacked in vertical direction using epitaxially grown SiGe/Si/SiGe/Si/SiGe layers on a Si substrate. Damascene gate process is adopted to make the gate-all-around (GAA) cell structure. Next to the gate, side-gate is made and device characteristics are controlled by the side-gate operations. By forming the virtual source/drain using the fringing field from the side-gate, short channel effect is effectively suppressed. Array design is also investigated for 3D NAND flash memory application.     

A novel P-channel nitride-trapping nonvolatile memory device with excellent reliability properties

A novel P-channel nitride trapping nonvolatile memory device is studied. The device uses a P/sup +/-poly gate to reduce gate injection during channel erase, and a relatively thick tunnel oxide (>5 nm) to prevent charge loss. The programming is carried out by low-power band-to-band tunneling induced hot-electron (BTBTHE) injection. For the erase, self-convergent channel erase is used to expel the electrons out of nitride. Experimental results show that this p-channel device is immune to read disturb due to the large potential barrier for hole tunneling. Excellent P/E cycling endurance and retention properties are demonstrated. This p-channel device shows potential for high-density NAND-type array application with high-programming throughput (>10 Mb/sec).     

A fully decoded 2048-bit electrically programmable FAMOS read-only memory

A floating-gate avalanche-injection m.o.s. (FAMOS) charge-storage device is used as the basic nonvolatile memory element. The memory is organized as 256 words of 8 bits, it is fully TTL compatible, and can be operated in both the static or dynamic mode. The memory array was successfully fabricated with silicon gate m.o.s. technology yielding functional devices with access times of 800 ns in the static mode and 500 ns in the dynamic mode of operation. The memory chip is assembled in a 24-lead dual-in-line package.     

Non‐volatile Ferroelectric Poly(vinylidene fluoride‐co‐trifluoroethylene) Memory Based on a Single‐Crystalline Tri‐isopropylsilylethynyl Pentacene Field‐Effect Transistor

A new type of nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (P(VDF‐TrFE)) memory based on an organic thin‐film transistor (OTFT) with a single crystal of tri‐isopropylsilylethynyl pentacene (TIPS‐PEN) as the active layer is developed. A bottom‐gate OTFT is fabricated with a thin P(VDF‐TrFE) film gate insulator on which a one‐dimensional ribbon‐type TIPS‐PEN single crystal, grown via a solvent‐exchange method, is positioned between the Au source and drain electrodes. Post‐thermal treatment optimizes the interface between the flat, single‐crystalline ab plane of TIPS‐PEN and the polycrystalline P(VDF‐TrFE) surface with characteristic needle‐like crystalline lamellae. As a consequence, the memory device exhibits a substantially stable source–drain current modulation with an ON/OFF ratio hysteresis greater than 10³, which is superior to a ferroelectric P(VDF‐TrFE) OTFT that has a vacuum‐evaporated pentacene layer. Data retention longer than 5 × 10⁴ s is additionally achieved in ambient conditions by incorporating an interlayer between the gate electrode and P(VDF‐TrFE) thin film. The device is environmentally stable for more than 40 days without additional passivation. The deposition of a seed solution of TIPS‐PEN on the chemically micropatterned surface allows fabrication arrays of TIPS‐PEN single crystals that can be potentially useful for integrated arrays of ferroelectric polymeric TFT memory.     

High‐Performance Top‐Gated Organic Field‐Effect Transistor Memory using Electrets for Monolithic Printed Flexible NAND Flash Memory

High‐performance top‐gated organic field‐effect transistor (OFET) memory devices using electrets and their applications to flexible printed organic NAND flash are reported. The OFETs based on an inkjet‐printed p‐type polymer semiconductor with efficiently chargeable dielectric poly(2‐vinylnaphthalene) (PVN) and high‐k blocking gate dielectric poly(vinylidenefluoride‐trifluoroethylene) (P(VDF‐TrFE)) shows excellent non‐volatile memory characteristics. The superior memory characteristics originate mainly from reversible charge trapping and detrapping in the PVN electret layer efficiently in low‐k/high‐k bilayered dielectrics. A strategy is devised for the successful development of monolithically inkjet‐printed flexible organic NAND flash memory through the proper selection of the polymer electrets (PVN or PS), where PVN/‐ and PS/P(VDF‐TrFE) devices are used as non‐volatile memory cells and ground‐ and bit‐line select transistors, respectively. Electrical simulations reveal that the flexible printed organic NAND flash can be possible to program, read, and erase all memory cells in the memory array repeatedly without affecting the non‐selected memory cells.     

P-channel Ge/Si Hetero-nanocrystal Based MOSFET Memory

The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunneling oxide T_ox=2nm and the dimensions of Si- and Ge-nanocrystal D_Si=D_Ge=5nm, the retention time of this device can reach ten years(~1×10~8s) while the programming and erasing time achieve the orders of microsecond and millisecond at the control gate voltage |V_g|=3V with respect to N-wells, respectively. Therefore, this novel device, as an excellent nonvolatile memory operating at room temperature, is desired to obtain application in future VLSI.     

Fully depleted silicon on insulator MOSFETs on (1 1 0) surface for hybrid orientation technologies

Effective memory performance of the nonvolatile memory/thin film transistor (NVM/TFT) devices needs good TFT characteristics. The reduction in leakage current of the TFT devices was accomplished with the gate offset (GOF) structure. A simplified fabrication process for the GOF NVM is introduced in this study using the insulator over-etching approach. Nonvolatile memory devices on glass using SiO₂/SiO_x/SiO_xN_y stack with an offset length of 0, 0.2, 0.4, and 0.6 μm were investigated. The highly selective etching process and the short offset length help to avoid the problem of the gate aluminum collapsing on the source/drain electrodes. The TFT characteristics of the GOF structures displayed the remarkable improvement in leakage from 1.1 × 10⁻¹¹ A, for the TFT without an offset region, to the low OFF current of 1.34 × 10⁻¹² A for the device with a 0.6 μm offset length. The longer offset length gave the lowest OFF current. The degradation in transconductance and the threshold voltage was negligible with the g_m values of about 3 × 10⁻⁶ S and ΔV_th of about 0.2 V, respectively. The switching characteristics remained similar for all the devices. Additionally, the GOF structures slightly enhanced the retention characteristics. The memory window of the NVM without the offset after a retention time of 10,000 s was 58%, lower than the over 69% of the GOF devices. Therefore, the application of the GOF structure to reduce the leakage of the NVM/TFT proved to be effective.     

Crack-guided effect on dynamic mechanical stress for foldable low temperature polycrystalline silicon thin film transistors

In the thin film transistors (TFTs) device research for foldable display, the degradation effect by the mechanical stress is crucial. Here, the crack position is critical for TFT reliability. However, it is difficult to characterize the crack position due to the random generation of the crack by mechanical stress. In this paper, the crack-guided low temperature polycrystalline silicon (LTPS) TFT test structures are fabricated and the crack-guided effects on mechanical stress of the tested TFT structure are analyzed. To strain on the foldable LTPS TFTs, 50,000 cycles of tensile and parallel direction dynamic mechanical stresses were applied with 2.5-mm bending radius. Based on the results, the generating crack position can be guided and controlled and also TFT reliability for foldable display can be enhanced.     

Programmable memory in organic field-effect transistor based on lead phthalocyanine

A nonvolatile organic field-effect transistor (OFET) with a polymeric electret as gate insulator and spun cast film of lead phthalocyanine (PbPc) as semiconductor channel is reported. Hysteresis induced by gate–bias stress was exploited to study nonvolatile memory effects. The observation of the hysteresis and memory window is proposed to originate from charge storage in the polymeric electret. The on state retention time for the OFET memory device is more than 5 h and the device can reproduce continuous write–read–erase–read switching cycles.     

Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal–Oxide–Semiconductor Devices Using II–VI Tunnel Insulators

This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal–oxide–semiconductor (MOS) device, and demonstrates the threshold voltage shift required in nonvolatile memory devices using a floating gate quantum dot layer. An InGaAs-based nonvolatile memory MOS device was fabricated using a high-κ II–VI tunnel insulator stack and self-assembled GeO _x -cladded Ge quantum dots as the charge storage units. A Si₃N₄ layer was used as the control gate insulator. Capacitance–voltage data showed that, after applying a positive voltage to the gate of a MOS device, charges were being stored in the quantum dots. This was shown by the shift in the flat-band/threshold voltage, simulating the write process of a nonvolatile memory device.     

Characterization of Ge2Sb2Te5 thin film transistor and its application in non-volatile memory

With the increasing requirement of high density memory technology, a new cell structure—1TR has received much attention. It consists of a single thin film transistor (TFT) with chalcogenide Ge₂Sb₂Te₅ as the channel material. In order to evaluate the feasibility of its application in the field of non-volatile memory, we take a further step in researching on the characteristics of GST-TFT. We fabricated a back-gate GST-TFT and investigated the output and transfer characteristics of its two states. The experimental results show that gate voltage can modulate the GST channel currents in both the amorphous and the crystalline states. Based on the experiments, we can expect that this novel device can ultimately lead to a new nonvolatile memory technology with even higher storage density.     

An integrated driving circuit implemented with p-type LTPS TFTs for AMOLED

Based on the technology of low temperature poly silicon thin film transistors (poly-Si-TFTs), a novel p-type TFT AMOLED panel with self-scanned driving circuit is introduced in this paper. A shift register formed with novel p-type TFTs is pro- posed to realize the gate driver. A flip-latch cooperated with the shift register is designed to conduct the data writing. In order to verify the validity of the proposed design, the circuits are simulated with SILVACO TCAD tools, using the MODEL in which the paramete...     

Effects of the timing of AC stress on device degradation produced by trap states in low-temperature polycrystalline-silicon TFTs

Device degradation under ac stress in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed with the density of trap states, electron-emission time, and electron-trapping time as foci. LTPS TFTs are shown to incur greater deterioration of characteristics under ac stress than silicon-on-insulator TFTs. Characteristics are more rapidly worsened as the falling time (t/sub f/) of gate pulses becomes shorter in the range below 1 ms. In addition, the degradation produced by a given number of pulses increases with the duration of the low level of the gate pulse in the range up to 1 ms. These behaviors are due to the slow emission of trapped electrons. On the other hand, the device degradation is independent of the duration of the high level of the gate pulse because the electrons are trapped quickly (in less than 1 /spl mu/s) once the level on the gate becomes high. The U-shaped distribution of trap-state density within the energy gap largely determines the dependence of the ac stress degradation on t/sub f/, since trapped electrons for which the emission time is longer than t/sub f/ are not emitted within the period of transient variation of gate voltage, and the number of electrons emitted after the gate has gone low increases with decreasing t/sub f/. Severe degradation is induced by ac stress conditions that correspond to electron emission from the trap states close to conduction band when the TFT is turned off.     

基于 P-Type 多晶硅TFT技术的集成型有源 OLED 驱动电路

低温多晶硅(LTPS:Low-temperature poly-Si)技术已经成为薄膜晶体管(TFT:thin film transistor)制作中最具吸引力的技术,并应用在AMOLED显示器中.P-type 技术能够简化 TFT 的制作过程.本文提出了一种应用 p-type 多晶硅 TFT的 AMOLED 驱动电路结构,包括栅极驱动器、数据驱动器以及像素阵列.数据驱动器采用分块方法,使得显示屏的输出线数大大减少.作者采用一种改进的 p-type 移位寄存器实现逐行选通的功能,并采用由 4 个 p-type 反相器级联构成的缓冲器来提高电路的驱动能力.为了验证上述电路结构的正确性,作者采用 HSPICE 软件进行仿真分析.结果表明,电路工作正常.利用韩国汉城国立大学及 Neo Poly 公司在多晶硅制作方面的优势,我们已经合作完成了应用上述电路结构的分辨率为96×3×128的有源 OLED 的制作.