Influence of buffer layer thickness on DC performance ofGaAs/AlGaAs heterojunction bipolar transistors grown on siliconsubstrates

The DC performance of GaAs/AlAs heterojunction bipolar transistors (HBTs) grown on silicon substrates with buffer layers ranging from 0 to 5 μm was investigated. Current gain, collector-emitter breakdown voltage, emitter-base and collector-base diode ideality factors, and breakdown voltages were measured as the buffer layer thickness was varied between 0 and 5 μm. The current gain steadily increases with increasing buffer layer thickness until the layer reaches 3 μm. However, the other DC parameters are relatively insensitive to the buffer layer thickness. A small-signal current gain of 60 is typically achieved for devices with 6×6-μm² emitters at a density of 6×10⁴ A/cm² when the buffer layer is ⩾3 μm     

A photodiode cell for applications to position and motionestimation sensors

An optical cell has been designed and fabricated using standard digital 1.6 μm CMOS technology. It has been designed for applications to sensors where the image acquisition time of fast moving objects or documents is of primary importance. The cell contains a photodiode working in storage mode and a shielded MOS capacitor acting as analog frame buffer. A chip prototype containing 64 linear arrays of 64 cells whose size is 36×36 μm² has been tested and measurements have proved the functionality down to microsecond-range of exposure times. By virtue of the proposed read-out technique, the sensor architecture provides simultaneous image acquisition of irregular moving objects allowing precise detection of position and motion     

A static power saving TTL-to-CMOS input buffer

This paper describes a TTL-to-CMOS input buffer that has no static power consumption for the typical TTL voltage level. The input buffer utilizes a feedback configuration to eliminate static power consumption that renders hysteresis characteristic. The hysteresis characteristic is equivalent to that of a Schmitt trigger and thus provides good noise immunity. A prototype circuit was implemented in a 0.8 μm CMOS process, and the through current is measured to be only 8.9 μA and 11.7 μA for the input of 0.8 V and 2.2 V (the worst case TTL level), respectively. The input buffer gives full-swing output upto 170 MHz when driving a minimum sized inverter with the worst case TTL level according to SPICE simulation     

Low-voltage class AB buffers with quiescent current control

This paper presents a simple class AB buffer which is suitable for low-voltage (1.5 V) applications. The proposed buffer uses an adaptive load to reduce the sensitivity of the quiescent current to the process variation. The main feature of this scheme is its simplicity. The circuit was fabricated in a 2.0 μm digital CMOS process. Experimental results demonstrate that the buffer can operate with a supply voltage below 2 V, and it has the capability to drive small resistive loads     

A 250-MHz skewed-clock pipelined data buffer

A synchronous dual-port memory employing a three-transistor (3T) dynamic cell has been designed for use as a high throughput embedded data buffer in digital switching and signal processing applications. Skewed-clock pipelining is used to achieve operation at frequencies as high as 250 MHz with a low register element count. The 3T cell provides separate read and write access ports while occupying less than half the area of a conventional dual-port SRAM cell. On-chip Hamming error correction coding (ECC) is used to enhance the fault tolerance of the memory, A 25-kb experimental prototype has been integrated in a 0.8-μm CMOS technology; it occupies a die area of 3800 μm×1600 μm and dissipates 420 mW while operating at 250 MHz     

A high-power CH3F laser for plasma diagnostics

A high-power, optically pumped, methyl fluoride laser operating at 496 μm has been developed for plasma diagnostic applications. An output power of 100 mW has been measured directly on a calorimeter. The high-pump power utilized in this experiment has also allowed the first observation of saturation in far-infrared output power resulting from severe vibrational bottlenecking. The effect of buffer gases in relieving this bottlenecking is described and compared to a simple rate-equation model     

A class-B output buffer for flat-panel-display column driver

Due to the large number of output buffers on a column driver chip of a flat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, large output swing, and wide operating voltage range class-B output buffer amplifier for driving the large column line capacitance in a flat-panel display. A comparator is used in the negative feedback path to eliminate quiescent current in the output stage. The proposed output buffer circuit was implemented in a 0.8 μm CMOS process. Its output voltage swing is from 1 V to the supply voltage. With 5 V supply and 600 pF load, the maximum tracking error is ±7 mV. The measured static current is 24 μA. The settling time for 4 V swing to within 0.2% is 8 μs, which is more than adequate for driving 1280×1024 pixels liquid crystal displays with 86 Hz frame rate and 256 gray levels in each color     

High temperature characteristics of GaAs MESFET devices fabricatedwith AlAs buffer layer

We have investigated the influence of AlAs buffer layers on MESFET drain leakage current at temperatures from 25-350°C. The experimental results show that subthreshold drain leakage current is substantially decreased with increasing AlAs layer thickness. For a 1 μm×200 μm MESFET with 2500 Å of AlAs buffer layer, we have obtained 78 μA of subthreshold drain leakage current at 350°C ambient temperature. This leakage current value is a factor of 2.5 improvement over the best previously reported results at 350°C     

A 2.5-GHz BiCMOS transceiver for wireless LAN's

A BiCMOS transceiver intended for spread spectrum applications in the 2.4-2.5 GHz band is described. The IC contains a low-noise amplifier (LNA) with 14 dB gain and 2.2 dB NF in its high-gain mode, a downconversion mixer with 8 dB gain and 11 dB NF, and an upconversion mixer with 17 dB gain and P_{-1 dB} of +3 dBm out. An on-chip local oscillator (LO) buffer accepts LO drive of -10 dBm with a half-frequency option allowed by an on-chip frequency doubler. Power consumption from a single 3-V supply is 34 mA in transmit mode, 21 mA in receive mode, and 1 μA in sleep mode     

Simplified Z-propagating DC bias stable TE-TM modeconvertor fabricated in Y-cut lithium niobate

A TE-TM mode converter, useful at either 0.632 or 0.840 μm, has been fabricated on y-cut LiNbO₃ by Ti indiffusion with the channel waveguide placed parallel to the z-axis. For TE polarized input, the maximum TM modulation depth is 97 percent at 0.632 μm with a 5-V (pp) drive and 99 percent at 0.840 μm with a 12-V (pp) drive. A similar device operating at 1.3 μm displays 98-percent TE-TM switching at 68 V. Operation involves only coplanar electrodes placed alongside the channel acting on the r₆₁ electrooptic coefficient. A separately deposited buffer layer is unnecessary. Testing indicates a substantially greater tolerance to electrode misalignment than afforded by similar structures formed in x-cut substrates. Data illustrating immunity to photorefractive drift in the presence of a DC bias voltage is presented for 0.840-μm wavelength operation     

一种应用于WLAN相位可调的本振缓冲器

该文提出了一种应用于WLAN相位可调的本振缓冲器,用于校准直接下变频收发机的I/Q两路不平衡。该电路通过开关输入MOS管源极的电容阵列,延迟本振信号,从而调节信号的相位。该文采用SMIC 0.18m工艺实现了4.8~6GHz的I/Q两路本振缓冲器的设计,其版图面积为650550m2。仿真结果表明,在5位控制字作用下,I或者Q路本振缓冲器的相移在0~8的范围内呈现近乎线性的变化,而本振缓冲器的输出功率的变化范围只有0.2dB。     

A versatile half-micron complementary BiCMOS technology formicroprocessor-based smart power applications

A modular, high density 0.5 μm Complementary BiCMOS technology with integrated high-voltage Lateral Diffused MOS (LDMOS) and conductivity modulated Lateral Insulated Gate Bipolar Transistor (LIGBT) structures designed for high performance, multi-functional integrated circuit applications is described. The advantages of VLSI processing and 0.5 μm compatible layout rules have been applied to the design and fabrication of the tight-pitch high-voltage devices without sacrificing the performance of 0.5 μm dual-poly (N+/P+) gate CMOS and complementary vertical bipolar transistors. Single chip integration of VLSI microprocessors with high-voltage and/or high-current input and output functions for “Smart Power” applications can be achieved using this technology     

Monolithic CCD imagers in HgCdTe

Charge-coupled device (CCD) infrared detector arrays in 5 μm cutoff HgCdTe have been demonstrated for low background applications. These fully monolithic 128 by 28 element CCD arrays incorporate time-delay-and-integrate (TDI) detection, serial readout multiplexing, charge-to-voltage conversion and buffer amplification in the HgCdTe detector chip. Operation of these devices at 77 K have produced average detectivity values exceeding 3×10¹³ cm-Hz^1/2/W for a background flux level of 6×10¹² photon/cm²-sec in the 3.0 μm to 5.5 μm spectral band. Overall performance data indicates the monolithic HgCdTe CCD to be a promising alternative to present midwave infrared hybrid focal plane array technology     

Low-voltage electronics for the stimulation of biological neuralnetworks using fully complementary BiCMOS circuits

This paper describes low-voltage neural stimulating circuitry developed using fully complementary BiCMOS (FC-BiCMOS) process technology for providing charge-balanced bipolar stimulating currents to tissue in the central nervous system. The electronics features an FC-BiCMOS buffer, a 7-b biphasic current-output digital-to-analog converter, a 14-b frequency divider, a nonoverlapping two-phase clock generator, and an auto timeout safety scheme while driving any two of eight selected sites from 0 to ±126 μA with ±2 μA resolution. The circuit area is 1.6 mm² in 3-μm features. Micropower circuit techniques allow the probe to dissipate <10 μW in standby and operate at 10 MHz from ±2.5 V supplies     

Design of 3:1 multiplexer standard cell

A new VLSI 3:1 multiplexer is presented. The proposed circuit is based on a double controlled tri-state buffer. A custom cell which can easily be added to the AMS 0.6 μm CMOS standard cell library has been developed. The new cell shows a propagation delay of ~780 ps and dissipates 5.2 μW/MHz     

Adaptive-biased buffer with low input capacitance

A new analogue buffer, which is a differential-pair-based level shifter followed by an adaptive-biased cascode source follower, is proposed. The structure exhibits low input capacitances, enhanced slew rate, high bandwidth and low distortion. The simulated results have shown input capacitance of 99.5 fF at 1 MHz, slew rate of 55.5 V/μs, -3 dB bandwidth of 37.9 MHz, and THD less than 1% for 1 Vpp input signal up to 6 MHz at a 100 kΩ//15 pF load. The buffer consumes 2.4 mW at 5 V supply in a 0.8 μm n-well CMOS technology     

Stacked-NMOS triggered silicon-controlled rectifier for ESDprotection in high/low-voltage-tolerant I/O interface

A stacked-NMOS triggered silicon-controlled rectifier (SNTSCR) is proposed as the electrostatic discharge (ESD) clamp device to protect the mixed-voltage I/O buffers of CMOS ICs. This SNTSCR device is fully compatible to general CMOS processes without using a thick gate oxide to overcome the gate-oxide reliability issue. ESD robustness of the proposed SNTSCR device with different layout parameters has been investigated in a 0.35 μm CMOS process. The HBM ESD level of the mixed-voltage I/O buffer with the stacked-NMOS channel width of 120 μm can be obviously improved from the original ~2 kV to be greater than 8 kV by this SNTSCR device with device dimensions of only 60 μm/0.35 μm     

A 1.2-μm BiCMOS sample-and-hold circuit with aconstant-impedance, slew-enhanced sampling gate

A new sampling gate circuit, with dual outputs functioning alternately in the track and hold modes, is integrated in an open-loop sample-and-hold circuit architecture achieving greater than 450-MHz small-signal input bandwidth and 100-MHz maximum sample rate. The sampling gate also incorporates slew enhancement techniques to achieve (+430 V/μs, -510 V/μs) slew rate and features a `built-in' buffer to maintain constant input impedance for both the track and hold modes, simplifying design of the front-end input buffer. Special on-chip clock generation circuits are used to minimize sampled pedestal (+4 mV). Power dissipation is less than 300 mW, including output driver. Measured harmonics are 58 dB down for a 2 V_p-p 20-MHz sine wave sampled at 100 MHz     

Weak inversion four-quadrant multiplier and two-quadrant divider

A four-quadrant multiplier and a two-quadrant divider are presented. The proposed circuits are implemented by MOSFETs operating in weak inversion and are therefore suitable for low voltage and low power applications. Their performances were confirmed by HSPICE simulation using a 0.8 μm CMOS process. The multiplier can operate under a ±0.75 V supply voltage and its linear input range is ~0.125 μA with error <2%. The input range of the divider is 0.5-2 μA and the error is <3% for divider current <60 nA     

A one-chip scalable 8*8 ATM switch LSI employing shared bufferarchitecture

The authors present a one-chip scalable 8×8 shared buffer switch LSI which includes a 256-cell buffer. Speedup, flow control, and input slot rotation functions are provided in order to interconnect LSIs for scaling-up without degrading cell loss rates. Computer simulations show that these functions bring a satisfactory result and can make the cell loss- rate for a Clos three-stage network superior to that for the output buffer switch which includes the same amount of buffer space. A 0.8 μm BiCMOS process is employed for this LSI. The total number of transistors is one million. This LSI has already been fabricated