MOSFET hot-carrier reliability improvement by forward-body bias

Active threshold voltage V/sub TH/ control via well-substrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and standby power requirements for CMOS technology beyond the hp65-nm node. In this letter, the impact of substrate bias V/sub SUB/ on hot-carrier reliability is presented. The impact varies with the gate length and body effect factor. These findings are explained, and the effects of future scaling are discussed using a quasi-two-dimensional model. Significant and important improvement in hot-carrier lifetime with forward-bias V/sub SUB/ can be expected for deeply scaled CMOS devices, making it an attractive method for extending the scalability of bulk-Si transistor technology.     

A novel technique for profiling the lateral n- dopingconcentrations of submicron LDD MOS devices

This paper reports a simple I-V method for the first time to determine the lateral lightly-doped source/drain (S/D) profiles (n^- region) of LDD n-MOSFETs. One interesting result is the direct observation of the reverse-short-channel effect (RSCE). It is observed that S/D n^- doping profile is channel length dependent if reverse short-channel effect exists as a result of the interstitial imperfections caused by Oxide Enhanced Diffusion (OED) or S/D implant. Not only the lateral profiles for long-channel devices but also for short-channel devices can be determined. One other practical application of the present method for device drain engineering has been demonstrated with a LATID MOS device drain engineering work. It is convincible that the proposed method is well suited for the characterization and optimization of submicron and deep-submicron MOSFETs in the current ULSI technology     

Performance and reliability evaluation of high dielectric LDDspacer on deep sub-micrometer LDD MOSFET

High dielectric LDD spacer has been proposed to achieve both reliability and performance improvement on the scaled LDD MOSFET's. However, the sidewall polyoxide and spacer bottom oxide required for process reliability issue will adversely limit the DC performance improvement gained by using high dielectric LDD spacer. AC performance is evaluated by the transconductance cutoff frequency determined by the transconductance, G_M and total gate capacitance, C_GG . For deep-submicron MOSFET's, the dominance of gate to source/drain overlap capacitance in C_GG has significant impact on the AC performance. The increase of C_GG due to the enhanced fringe field from high dielectric LDD spacer significantly dominates over the increase of transconductance, and then deteriorates the AC performance. As the reliability issue is concerned, the key doping profile, N^- source/drain lateral diffusion profile was obtained from the two dimensional process simulator SUPREM-IV corresponding to wide range of LDD N^- doses. The optimized N ^- dose designed for hot carrier reliability issue (under V _GS-V_T=0.5 V_DS operation) is located around 2×10¹³ cm^-2 for both conventional LDD (denoted as OLDD in this paper) and high dielectric LDD (HLDD) devices. However, the improvement achieved by using HLDD instead of OLDD devices is then turned out to be insignificant under this optimized N^- dose condition     

A role of source n-region in LDD MOSFET's

A new role of source n^-region in lightly doped drain (LDD) MOSFET's is presented. This is "bipolar action" reduction due to n^-source resistance, which determines the drain-sustaining voltage. Also, the n^-resistance can be directly measured by using this phenomenon.     

Sloped-junction LDD (SJLDD) MOSFET structures for improvedhot-carrier reliability

Sloped-junction lightly doped drain (SJLDD) structures, for 0.5- μm channel length MOSFETs, which exhibit exponential improvement in lifetime under high-field stress with source-drain implant energy are discussed. The improved lifetime correlates with reduced drain electric fields and increased depth of peak avalanche below the silicon-silicon dioxide as determined by simulation. The results present an interesting instance where the substrate current fails as a hot-carrier monitor and provide indirect evidence of a energy-dependent electron mean-free path decreasing from the known 5.7 nm at the impact ionization threshold to less than 3.2 nm at kinetic energy of about 4.6 eV     

MOSFET degradation due to hot-carrier effect at high frequencies

Hot-carrier-induced degradation due to AC stress on short-channel MOSFETs is discussed. It is observed that pulsed gate voltage stressing with a short falltime (0.7 ns) can cause additional lifetime degradation in the form of drain-current reduction. The AC-enhanced degradation is more pronounced at higher frequencies     

A new concept of p-(n-)/p-(n ) thin-film epitaxial silicon wafers for MOS ULSI's that ensuresexcellent gate oxide integrity

A new concept of epitaxial silicon (Si) wafers (NC epi) in which p ^-(n^-) thin-film layers are grown on p^-(n^-) Czochralski (CZ)-Si substrates (substrate resistivity: approximately 10 Ω cm) is proposed for metal oxide semiconductor (MOS) ultra large-scale integrated circuits (ULSI's) as a starting material. A thickness of 0.3-1 μm for the epitaxial layer (p ^-/p^- structure) is shown to be sufficient for improving the gate oxide integrity for MOS-ULSI's. The epitaxial layer grown on Si substrate greatly reduces weak spots in the gate oxide layer by covering microdefects in the CZ-Si represented by the crystal originated particle (COP). The p^-/p^$thin-film epitaxial structure results in very controlled resistivity for the electrically active region in the device, which in turn results in a lower growth cost and higher feasibility for use in current ULSI's. The features of NC epi in combination with proximity gettering is presented. An application of NC epi in shallow-trench isolation processes is discussed, considering the retrograde-type well-tub. The amenability of epitaxial wafers to wafer enlargement (over 300 mm) is discussed to eliminate the bad effects of COP     

FinFET and MOSFET preliminary comparison of gate oxide reliability

In this work, the influence of gate oxide reliability on N channel FinFET and MOSFET characteristics has been preliminary compared. For similar oxide damage, the results show that the oxide wear out has larger effects on the functionality of the FinFET than on the MOSFET.     

轻掺杂漏(LDD)MOSFET的数值模拟

轻掺杂漏(LDD)MOSFET是一种已用在VLSI中的新型MOSFET结构.为了有效地进行LDD MOSFEI的优化设计,我们在二维数值模拟器MINIMOS的基础上,修改了边界条件及输入输出格式,考虑了轻掺杂区的杂质分布,研制成功了一种既适用于常规以MOSFET,又适用于LDD MOSFET的二维数值模拟程序FD-MINIMOS.应用该程序对LDD MOSFET的一系列直流特性模拟的结果表明,不同的轻掺杂浓度对于抑制沟道电场及热电子效应具有不同的效果,为轻掺杂区优化设计提供了重要信息.     

An improvement of hot-carrier reliability in the stackednitride-oxide gate n- and p-MISFET's

Thin LPCVD stacked nitride-oxide gate MISFET's offer the potential for high current drive as a consequence of the high permittivity of the nitride. However, thin nitride-oxide films have yet to be used in actual MISFET's for LSI products because thin nitride films have poor masking ability during re-oxidation and low reliability under hot-carrier stress. We have investigated improvements to thin LPCVD stacked nitride-oxide films as regards masking ability during re-oxidation and hot-carrier reliability. The method proposed to improve film quality is densification through high-temperature rapid thermal processes and its effectiveness has been tested. Simple rapid thermal annealing (RTA) did not improve the film quality at all. On the other hand, rapid thermal nitridation (RTN) on the deposited nitride film improved it considerably. The reason for the improvement by RTN was investigated     

Impact of MOSFET gate oxide breakdown on digital circuit operationand reliability

The influence of FET gate oxide breakdown on the performance of a ring oscillator circuit is studied using statistical tools, emission microscopy, and circuit analysis. It is demonstrated that many hard breakdowns can occur in this circuit without affecting its overall function. Time-to-breakdown data measured on individual FETs are shown to scale correctly to circuit level. SPICE simulations of the ring oscillator with the affected FET represented by an equivalent circuit confirm the measured influence of the breakdown on the circuit's frequency, the stand-by and the operating currents. It is concluded that if maintaining a digital circuit's logical functionality is the sufficient reliability criterion, a nonzero probability exists that the circuit will remain functional beyond the first gate oxide breakdown. Consequently, relaxation of the present reliability criterion in certain cases might be possible     

Features and mechanisms of the saturating hot-carrier degradationin LDD NMOSFETs

Propagation of defects from the sub-spacer region to the gate-overlapped LDD region in NMOSFETs is modeled using measurements and 2-D device simulation. It is argued that the saturation of degradation is caused by the saturating nature of this degradation length, as opposed to decreasing lateral electric field maxima (E_m) or increasing barrier height (φ_it) to defect creation. Two stage hot-carrier degradation was observed in our LDD NMOSFETs. The early mode (1000-3000 s) of the degradation is characterized by a sharp rate of degradation of the linear transconductance (g_m), and a reduction in the substrate current (I_B). In order to locate and quantify defects produced in this early mode degradation phase, we use the results of a combination of the floating gate technique and simultaneous measurements of the reverse (source and drain interchanged) saturation g_m's. These results help us build a 2-D simulation framework involving trapped negative charges in the oxide in the drain-side gate-edge region, partly under the gate and partly in the spacer region. We then use 2-D simulation and other measurements such as linear and saturation current degradation, I_B degradation, and charge pumping to confirm the location of the defects and help estimate their quantity. Simulation results also help us build an analytical model for defect propagation from the early mode to the late mode. The analytical model is seen to explain many features of the saturating nature of hot-carrier degradation     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

A reassessment of ac hot-carrier degradation in deep-submicrometer LDD N-MOSFET

In deep submicrometer N-MOSFET, a "backdrop" of substantial defect generation by the quasi-static V/sub g/=V/sub d/ stress phase is shown to significantly influence the accuracy of interpretation of ac stress data. If neglected, a severe overestimation of ac stress induced degradation would result. Through an approach that eliminates this damage component from the overall ac stress damage, increased parametric shifts, associated with the gate pulse transition phase, are found to occur in different time windows, delineated by the relative importance of hot-hole and hot-electron induced damage at different stages of the stress, the interaction between the two damages at specific stages of the stress, as well as the sensitivities of the device parameters to the spatial evolution of the two damages.     

Source-to-drain nonuniformly doped channel (NUDC) MOSFET structuresfor high current drivability and threshold voltage controllability

The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V_th lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V_th lowering at 0.4-μm gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4-μm gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4-μm gate length     

Characteristics of siliconn+-n--n+ diode with sub-micrometer n- region

In this paper, the I-V characteristics of silicon n⁺-n ^--n⁺ diode are investigated as a parameter of the length of the n^- region. This diode with shorter n^- region than 1 μm has the ohmic characteristics until reaching high electric field in spite of the existence of numerous space-charges in the n^- region, for the first time in this report. This conductance of the diode is inversely proportional to the third power of the length of the n^- region. The experimental results are in good agreement with an analytical calculation including the diffusion term of carriers injected from the n+ regions to the n^- region. However, the diode with longer n^- region than 2 μm shows the space-charge-limited conduction which is the same as earlier reports     

A theoretical study of gate/Drain offset in LDD MOSFET's

A semi-quantitative model for the lateral channel electric field in LDD MOSFET's has been developed. This model is derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile. A field reduction factor, indicating the effectiveness of an LDD design in reducing the peak channel field, is used to compared LDD structures with, without, and with partial gate/drain overlap. Plots showing the trade-off between, and the process-dependencies of, the field reduction factor (FRF) and the series resistance are presented for the three cases. Structures with gate/drain overlap are found to provide greater field reduction than those without the overlap for the same series resistance introduced. This should be considered when comparing the double-diffused and spacer LDD structures. It is shown that gate/drain offset can cause the rise of channel field and substrate current at large gate voltages. Good agreement with simulations is obtained.     

Empirical model for the low-frequency noise of hot-carrier degradedsubmicron LDD MOSFETs

This paper discusses the empirical low-frequency (LP) noise behavior of hot-carrier degraded Lowly-Doped Drain (LDD) n-MOSFETs, which have been fabricated in a 0.7-μm CMOS technology. It is shown that the increase of the noise spectral density follows a t^0.3 power law dependence with stress time. Additionally, an empirical relationship will be shown between the input-referred noise spectral density S_VG and the transconductance g_m of the stressed devices. The practical consequences of this exponential dependence will be briefly discussed     

Improved device performance and reliability in high /spl kappa/ HfTaTiO gate dielectric with TaN gate electrode

The device performance and reliability of higher-/spl kappa/ HfTaTiO gate dielectrics have been investigated in this letter. HfTaTiO dielectrics have been reported to have a high-/spl kappa/ value of 56 and acceptable barrier height relative to Si (1.0 eV). Through process optimization, an ultrathin equivalent oxide thickness (EOT) (/spl sim/9 /spl Aring/) has been achieved. HfTaTiO nMOSFET characteristics have been studied as well. The peak mobility of HfTaTiO is 50% higher than that of HfO/sub 2/ and its high field mobility is comparable to that of HfSiON with an intentionally grown SiO/sub 2/ interface, indicative of superior quality of the interface and bulk dielectric. In addition, HfTaTiO dielectric has a reduced stress-induced leakage current (SILC) and improved breakdown voltage compared to HfO/sub 2/ dielectric.     

Poly-Si gate electrodes for AlGaN/GaN HEMT with high reliability and low gate leakage current

AlGaN/GaN HEMT with a BF₂-implanted polycrystalline Si gate has been characterized through comparison to TiN gate electrodes. Positive threshold voltage (V_th) shift was observed with the addition of F ions, which in turn degraded the effective electron mobility (μ_eff) by diffusion into the AlGaN/GaN interface and GaN layer. A large reduction in gate leakage current (J_g) was achieved and the property was maintained even after strong reverse-bias stressing. No additional degradation in μ_eff was observed, suggesting the formation of a stable poly-Si/AlGaN interface. Therefore, poly-Si gate electrodes have advantages in reducing the J_g and robustness against reverse-bias stressing.