An enhanced folded cascode Op-Amp using positive feedback and bulk amplification in 0.35 μm CMOS process

In this paper a new operational amplifier is presented which is based on the conventional folded cascode Op-Amp structure. A new method of positive feedback is used to increase dc-gain. This method does not limit the range of the output voltage swing. True performance of the Op-Amp in higher output voltage swings is another advantage of the proposed Op-Amp in comparison with the conventional structures. Bulk amplification and positive feedback are used to improve the Op-Amp specifications. Proposed structure has been simulated by HSPICE software using level 49 parameters (BSIM3v3) in a typical 0.35 μm CMOS technology. The HSPICE simulation confirms the theoretical estimated improvements.     

Multipath recycling method for transconductance enhancement of folded cascade amplifier

A multipath recycling method to enhance transconductance of the folded cascode amplifier is presented in this paper. The proposed method utilizes two idle paths to conduct small signal current, which leads to significant enhancement of transconductance compared to conventional folded cascade structure. Moreover, the improved performance is almost at no expense of power dissipation. The proposed multipath recycling and the conventional amplifiers are all designed in UMC 0.18 μm CMOS technology. Simulation results demonstrate that the transconductance of the proposed amplifier is improved by 450% and dc gain enhances 16 dB when compared with the folded cascode counterpart.     

Design and analysis of DC gain and transconductance boosted recycling folded cascode OTA

A new technique for improving the transconductance and low frequency output impedance of recycling folded cascode (RFC) amplifiers is presented. This enhancement was achieved by using a positive feedback and upgrading the recycling structure. The new structure profits from better transconductance, slew rate, and DC gain in comparison with conventional folded cascode (FC) amplifier. Moreover, the input referred noise is reduced and the phase-margin improved. The enhanced amplifier, simulated in 0.18 μm CMOS technology, exhibits a DC gain enhancement of 16.3 dB as well as 115.5 MHz increase in gain bandwidth compared to conventional FC configuration. The amplifier consumes 360 μW @ 1.2 V which makes it suitable for low-voltage applications.     

An Adaptive Biased Single-Stage CMOS Operational Amplifier with a Novel Rail-to-Rail Constant-<Emphasis Type="Italic">g</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript> Input Stage

Using rail-to-rail (R-R) swing analog circuits has become almost mandatory in the design of low supply voltage circuits. In this paper, a new architecture for constant-g_m rail-to-rail input stages is presented. The design features a less than 5% deviation in g_m over the entire range of the input common-mode voltage. Furthermore, a new structure for folded cascode amplifier based on the use of a floating current source is presented. By employing these techniques, a low-power operational amplifier (op-amp) with 100 MHz unity-gain bandwidth, 106 dB gain, 60^∘ phase margin, 2.65 V swing, and 6.4 nV/✓Hz input-referred noise with rail-to-rail input common-mode range is realized in a 0.8 μ m CMOS technology. This amplifier dissipates 10 mW from a 3 V power supply.     

A transconductance enhanced recycling structure for folded cascode amplifier

This letter is to present a transconductance enhanced recycling structure for folded cascode amplifier. The proposed structure introduces a positive feedback path to achieve a significant boost in transconductance without increasing power or area consumption. A folded cascode amplifier using the proposed structure was implemented in SMIC standard 65 nm CMOS process. Simulation results show that the proposed amplifier achieves 400% improvement in gain-bandwidth and 16.6 dB boost in DC gain compared to the conventional folded cascode.     

The CMOS gain-boosting technique

The gain-boosting technique improves accuracy of cascoded CMOS circuits without any speed penalty. This is achieved by increasing the effect of the cascode transistor by means of an additional gain-stage, thus increasing the output impedance of the subcircuit. Used in opamp design, this technique allows the combination of the high-frequency behavior of a single-stage opamp with the high DC-gain of a multistage design. Bode-plot measurements show a DC-gain of 90 dB and a unity-gain frequency of 116 MHz (16 pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding with a closed-loop bandwidth of 18 MHz (35 pF load) and a settling accuracy better than 0.03 percent. A more general use of this technique is presented in the form of a transistor-like building block: the Super-MOST. This compound circuit behaves as a normal MOS-transistor but has an intrinsic gain gm.ro of more than 90 dB. The building block is self-biasing and therefore very easy to design with. An opamp consisting of only 8 Super-MOST's and 4 normal MOST's has been measured showing results equivalent to the design mentioned above.     

Double recycling technique for folded-cascode OTA

Presented is a double-recycling folded cascode (DRFC) operational transconductance amplifier (OTA), demonstrating another phase of significant performance enhancement over the existing folded cascode, recycling folded cascode and improved recycling folded cascode counterparts. Theoretical treatments and computer simulations under the same 65 nm CMOS technology justify fairly the merits of the proposed DRFC OTA.     

Enhancing general performance of folded cascode amplifier by recycling current

A modification to the conventional folded cascode transconductance amplifier is proposed. The proposed amplifier has the benefit of achieving a given set of design specifications while consuming a fraction of the power compared to the conventional folded cascode. Moreover, the proposed modification is robust even for low voltage applications.     

Capacitor Cross-Coupled Fully-differential CMOS Folded Cascode LNAs with Ultra Low Power Consumption

This paper proposes a fully-differential folded cascode low noise amplifier (LNA) for 5.5 GHz receiver in 180 nm CMOS technology. By improving folded cascode with an additional inductance connected at the gate of CG stage to cancel parasitic capacitance and then employing capacitor cross-coupled technique as a negative feedback in the proposed LNA, the performance of the LNA can be improved significantly in terms of gain (S21) and noise figure (NF) compared with the conventional fold cascode LNA. Furthermore, the DC power consumption of the LNA is further reduced with forward body bias topology. The measurements show the proposed LNA achieves 16.5 dB power gain, a NF of 1.53 dB, good input/output matching with the S11 and S22 are less than \(-\) 15 dB. And the operating voltage is only 0.5 V with ultra-low power consumption of 0.89 mW.     

Large bandwidth BiCMOS operational amplifiers for SC videoapplications

A single-ended and a fully differential broadband BiCMOS operational amplifier for switched-capacitor video applications are presented. The amplifiers feature a folded cascode gain stage with a current source as output load. For the single-ended amplifier the current mirroring is accomplished with a modified bipolar Wilson current mirror at the output of the differential pair. Symbolic expressions for the transfer functions for both amplifiers are derived. The amplifiers are integrated in an analog 1 μm BiCMOS process with an active die area of 0.72 mm² and 0.96 mm² for the single-ended and the fully differential amplifier, respectively. For both amplifiers a DC-gain of 68 dB and a unity gain frequency greater than 250 MHz was measured for a power supply voltage of 5 V     

Self-biasing of folded cascode CMOS op-amps

In cascode CMOS op-amps a large number transistors are biased using independent standard bias circuits. This results in numerous drawbacks, namely, an area and power overhead, and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no bias voltages other than the two supply rails. The resulting self-biased op-amps are free from the above mentioned drawbacks and exhibit the same performance as existing folded cascode op-amps. This is achieved by following transistor sizing constraints derived through detailed circuit analysis. The technique is applied to an existing high performance op-amp. Simulation results show that the high performance is maintained while nine bias voltages are eliminated.     

改进型折叠式共源共栅运算放大器电路的设计

在套筒式共源共栅、折叠式共源共栅运放中,折叠式共源共栅运算放大器凭借较大的输出摆幅和偏置电压的较低等优点而得到广泛运用。但是,折叠式的这些优势是以牺牲较大的功耗、较低的电流利用率而换取的。本文以提高电流利用率为着手点设计了一种改进的折叠式共源共栅运算放大器,在相同的电压和负载下改进的折叠式共源共栅运算放大器能显著提升跨导、压摆率和噪声性能。仿真结果表明在相同功耗和面积的条件下,改进的折叠式共源共栅运算放大器的单位增益带宽和压摆率是折叠式共源共栅运放的3倍。     

A feedforward technique with frequency-dependent current mirrorsfor a low-voltage wideband amplifier

A feedforward technique using frequency-dependent current mirrors for a low-voltage wideband amplifier is presented. In the conventional single-stage wideband amplifiers, the folded cascode structure is used. However, the common-gate transistor requires an additional V_{DS sat} and reduces the available output voltage range. In this study the cascode structure is avoided; instead, a frequency-dependent current mirror, whose input impedance becomes higher for a higher frequency, is used to form the feedforward path from the input of the current mirror with a feedforward capacitor. This technique is effective to improve a 100 MHz-1 GHz frequency characteristic of the amplifier. The amplifier has been fabricated using the standard 0.8 μm CMOS process. The phase margin is improved from 46-66° without sacrificing the unity gain frequency of 133 MHz compared with the amplifier without this technique. The amplifier operates at 2.5 V power supply voltage and consumes 12 mW     

适用于高阶∑△调制器的全差分运算放大器的设计

比较了增益自举式共源共栅、折叠式共源共栅和套筒式A／A类三种常用的运算放大器结构．提出了一种可用于各种高阶∑△调制器的全差分运算放大器。采用SIMC0．35μm标准CMOS工艺．完成了含共模反馈电路的全差分套筒式运算跨导放大器的设计。仿真结果表明放大器的直流增益为84．5dB,单位增益带宽为199MHz,相位裕度为51°,电路工作可靠,性能优良。     

Design of InP DHBT power amplifiers at millimeter-wave frequencies using interstage matched cascode technique

In this paper, the design of InP DHBT based millimeter-wave(mm-wave) power amplifiers(PAs) using an interstage matched cascode technique is presented. The output power of a traditional cascode is limited by the early saturation of the common-base(CB) device. The interstage matched cascode can be employed to improve the power handling ability through optimizing the input impedance of the CB device. The minimized power mismatch between the CB and the common-emitter(CE) devices results in an improved saturated output power. To demonstrate the technique for power amplifier designs at mm-wave frequencies, a single-branch cascode based PA using single-finger devices and a two-way combined based PA using three-finger devices are fabricated. The single-branch design shows a measured power gain of 9.2 dB and a saturated output power of 12.3 dBm at 67.2 GHz and the two-way combined design shows a power gain of 9.5 dB with a saturated output power of 18.6 dBm at 72.6 GHz.     

Adaptive double recycling folded cascode amplifier

Analog Integrated Circuits and Signal Processing - A new structure for improving the performance of recycling folded cascode (RFC) operational transconductance amplifier (OTA) is presented. The...     

Determination of gate-bias dependent source/drain series resistance and effective channel length for advanced MOS devices

In this paper, an improved method for determining the gate-bias dependent source and drain series resistances R_D and effective channel length L_eff = L_M − ΔL (L_M is the mask channel length and ΔL is the channel length reduction) of advanced MOS devices is developed for the purpose of providing a better accuracy for the modeling of the current–voltage characteristics of LDD MOSFETs operating from 25 to 120 °C. Our results show that both ΔL and R_SD decrease with increasing gate-bias, but increase with increasing temperature. In addition, the gate-bias dependence of ΔL and R_SD becomes weaker as the temperature rises. Experimental data obtained from devices fabricated using the 0.14 and 0.09 μm DRAM technologies are included in support of the theoretical work developed.     

异质栅氧化层轻掺杂漏石墨烯纳米条带p-i-n隧穿场效应管量子输运特性的研究

We perform a theoretical study of the effects of the lightly doped drain （LDD） and high-k dielectric on the performances of double gate p-i-n tunneling graphene nanoribbon field effect transistors （TFETs）. The models are based on non-equilibrium Green＇s functions （NEGF） solved self-consistently with 3D-Poisson＇s equations. For the first time, hetero gate dielectric and single LDD TFETs （SL-HTFETs） are proposed and investigated. Simulation results show SL-HTFETs can effectively decrease leakage current, sub-threshold swing, and increase on-off current ratio compared to conventional TFETs and Si-based devices; the SL-HTFETs from the 3p ＋ 1 family have better switching characteristics than those from the 3p family due to smaller effective masses of the former. In addition, comparison of scaled performances between SL-HTFETs and conventional TFETs show that SL-HTFETs have better scaling properties than the conventional TFETs, and thus could be promising devices for logic and ultra-low power applications.     

A power-efficient improved recycling folded cascode amplifier

An improved recycling folded cascode amplifier for wide-bandwidth ΣΔ modulator is presented in this article. The proposed amplifier introduces internal positive-feedback pairs to achieve a significant boost in transconductance and DC gain without increasing power or area budget. The proposed recycling folded cascode amplifier was implemented in SMIC standard 65?nm CMOS process. Compared to other recycling folded cascode structures, simulation results show that the proposed amplifier achieves the enhancement of gain-bandwidth and DC gain with the best figure-of-merits.