OFDM系统中同步算法的FPGA 实现

给出了一种用于 OFDM 系统中可同时完成帧起始位置估计和载波频偏估计／补偿的同步算法及其 FPGA 实现方法。采用量化的方法对该不需要额外同步序列的估计算法进行了改进,提高了载波频偏的估计精度,并在数字域进行了频偏校正。在硬件实现上,利用 CORDIC 算法能够有效计算三角函数的特点,把频偏估计和频偏校正过程中的反正切运算和角度旋转操作转化成加法和移位操作,实现了计算精度、运算速度和硬件资源利用三方面性能的兼顾。     

高精度正余弦函数的FPGA实现

在研究CORDIC算法的数学基础上,采用流水线的硬件结构实现了该算法,并在Ahera公司的FPGA芯片上进行了验证,使正余弦函数的计算达到了实时性、高精度的要求.该设计模块完全支持超过360°的大角度数据输入,多数数据精度达到了10-9,时钟频率可以达到233.2 MHz.测试结果表明,该系统具有较高的精确度和稳定性.     

Computationally Efficient Architecture for Accurate Frequency Estimation with Fourier Interpolation

A simplified DFT-based algorithm and its VLSI implementation for accurate frequency estimation of single-tone complex sinusoid signal are investigated. The proposed algorithm estimates frequency by interpolation using Fourier coefficients. It consists of a coarse search followed by a fine search, and its performance closely achieves the Cramer–Rao low bound (CRLB) even in low SNR region. Moreover, a pipelined triple-mode CORDIC architecture is designed to efficiently support complex multiplication, complex magnitude calculation and real division. The triple-mode CORDIC-based radix-4 architecture is employed for the hardware implementation of the frequency estimator, and is suitable for not only fast Fourier transformation but also accurate frequency estimation. A frequency estimator with 1024-point samples is implemented and verified on FPGA. It works at 215 MHz on a Xilinx XC6VLX240T FPGA device, and uses up 4,161 registers and 6,986 slice LUTs. ASIC synthesis results show that it requires an area of 60K equivalent NAND2 gates with a clock rate of 500 MHz at SMIC 0.18 μm technology. The whole latency of the frequency estimator is 2336 cycles. The proposed architecture provides a good trade off between hardware overhead, estimation performance and computation latency.     

基于低硬件复杂度、高速CORDIC的SVD模块设计与实现

为降低实现高阶矩阵SVD时的硬件复杂度和计算延时,本文改进了CORDIC迭代结构,设计了一种用于SVD的低硬件复杂度、高速CORDIC计算单元.本文以2×2矩阵为例,基于XilinxVirtex6硬件平台设计并实现了使用优化后CORDIC计算单元的SVD模块,在19bit位宽下吞吐率达25.9Gbps.对比Xilinx IP core中同类模块,本文设计节省27.6%寄存器,27.7%查找表,实时性提高14%.对高阶矩阵,本文给出资源消耗趋势曲线,可证明优化后CORDIC计算单元能降低16阶矩阵SVD模块约40%的硬件复杂度.     

突发OFDM系统中同步算法的FPGA实现

根据突发OFDM系统的特点,提出了一种具有实用价值的同步实现方法。具体分析了突发OFDM系统中利用PN序列联合实现符号定时同步和小数频偏同步的算法,并阐述基于FPGA的实现过程。由Verilog HDL语言描述的同步模块由复数乘法模块,求和累加模块,比较判断模块和CORDIC模块等构成。系统采用Xilinx ISE 10.1来完成开发,同时给出了其在ModelSim SE 6.2b下的仿真结果,结果表明该方案是完全可行的。     

Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos

This article presents an architecture for the fractional motion estimation (FME) of the H.264/AVC video coding standard focusing in a good tradeoff between the hardware cost and the video quality. The support to FME guarantees a high quality in the motion estimation process. The applied algorithmic simplifications together with the multiplierless implementation and with a well balanced pipeline allow a low cost and a high throughput solution. The architecture was also designed to avoid redundant external memory accesses when computing the FME. The design was divided in two main modules: integer motion estimation (with diamond search algorithm) and fractional refinement (half-pixel and quarter-pixel interpolation and search). The designed architecture was described in VHDL and synthesized to an Altera Stratix III FPGA. The architecture is able to reach 260 MHz when running in the target FPGA. In worst case scenario, this operation frequency allows a processing rate of 43 HD 1080p (1,920 × 1,080 pixels) frames per second, surpassing the requirements for real time processing. In comparison to related works, the developed architecture was able to achieve a good tradeoff among hardware costs, video quality and processing rate.     

Joint low‐complexity equalization and CFO estimation and compensation for UWA‐OFDM communication systems

Frequency synchronization has a great importance in preserving the performance of the underwater acoustic (UWA) orthogonal frequency division multiplexing (OFDM) systems. The carrier frequency offset (CFO) estimation can be blind or data‐aided. In this paper, the Zadoff‐Chu (ZC) sequences are used for OFDM synchronization in UWA communications, and they are compared with different data‐aided algorithms. We propose a low‐complexity algorithm for CFO estimation based on ZC sequences. Also, a joint equalization and CFO compensation scheme for UWA‐OFDM communication systems is presented. Simulation results demonstrate that the proposed CFO estimation algorithm allows estimation of the CFO accurately with a simple implementation in comparison with the traditional schemes. Also, the performance of the UWA‐OFDM system can be preserved in the presence of frequency offsets.     

MU-MIMO-OFDM上行中基于部分频偏预补偿的频偏同步

在MU-MIMO-OFDM上行链路中,载波频偏的估计和补偿均需要信道信息,而利用频域导频信号估计频偏和信道会受到子载波间干扰ICI)的影响.本文提出了一种部分频偏预补偿机制,可以使得快速傅里叶变换(FFT)之后接收信号中的ICI功率最小,从而在不改变频偏和信道估计算法的前提下提高估计精确度.为了求解预补偿频率,文中首先对信号中的ICI建模,接着通过最优化问题明确ICI功率与预补偿频率间的关系,最后得到了近似最优解的闭合表达式.通过仿真验证,使用了部分频偏预补偿机制之后,频偏与信道估计的误差将明显降低.     

先进音频编码中MDCT的新型递归结构及其FPGA设计

文章以新型的MDCT递归算法为基础，首先给出了一种主要模块分时共享、数据流同步多路处理的改进型并行处理结构，其可以高效地应用于国际音频标准MPEG-2以及MPEG-4的先进音频编码（AAC）当中。另外，针对递归实现结构高度模块化和较强规则性的特点，进行了FPGA的设计和仿真，结果表明：改进后的处理结构在增加少量硬件模块的条件下．大大提高了运算速度。     

基于流水线CORDIC算法的数字下变频实现

数字下变频的FPGA实现通常都是基于查表的方法，为了达到高精度要求，常常需要耗费大量的ROM资源去建立庞大的查找表。文中提出了一种基于流水线CORDIC算法的数字下变频实现方案，可有效地节省FPGA的硬件资源，提高运算速度。文章最后给出了该方案的精度分析和实验的仿真结果。     

Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks

This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8?×?N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.     

OFDM盲载波间干扰抑制与同步算法研究

针对载波频偏引起的子载波间干扰问题,提出一种基于独立分量分析的OFDM载波频率同步算法。本算法直接实现载波频率同步,可以避免基于导频机制的频偏估计和由频偏估计误差带来的频谱效率降低与性能损失。首先建立含频偏OFDM独立分量分析模型,然后从最大似然原则得到分离的代价函数,结合自然梯度优化得到OFDM源信号实现载波频率同步。理论分析表明,提出的算法不仅具有基于最大似然的频偏补偿性能而且提高了系统的输出信噪比。最后,仿真分析证明了算法的有效性。      

一种合并状态度量计算的高效并行Turbo码译码器结构设计及FPGA实现

为满足无线通信中高吞吐、低功耗的要求,并行译码器的结构设计得到了广泛的关注。基于并行Turbo码译码算法,研究了前后向度量计算中的对称性,提出了一种基于前后向合并计算的高效并行Turbo码译码器结构设计方案,并进行现场可编程门阵列(field-programmable gate array,FPGA)实现。结果表明,与已有的并行Turbo码译码器结构相比,本文提出的设计结构使状态度量计算模块的逻辑资源降低50%左右,动态功耗在125 MHz频率下降低5.26%,同时译码性能与并行算法的译码性能接近。     

基于CORDIC算法2FSK调制器的FPGA设计

频移键控（FSK）是用不同频率的载波来传递数字信号,并用数字基带信号控制载波信号的频率。提出一种基于流水线CORDIC算法的2FSK调制器的FPGA实现方案,可有效地节省FPGA的硬件资源,提高运算速度。最后,给出该方案的硬件测试结果,验证了设计的正确性。     

基于CORDIC算法的线性调频直接数字合成实现

本文介绍了一种应用CORDIC算法的线性调频直接数字合成(DDS)的实现方法。由于DDS输出的余弦波形直接由极坐标系中的幅度值和角度值确定,而CORDIC算法将极坐标系直接转换为包含正、余弦值的直角坐标系,从而实现频率数字调制。通过计算机仿真和FPGA硬件实现表明,采用这种算法的DDS是高精度和高效的。     

基于CORDIC算法的数字下变频

采用CORDIC算法设计实现数字下变频（DDC）。该设计方法克服了传统的数控振荡器（NCO）查找表（LUT）大的缺点,且该算法模块同时实现数控振荡器和混频器的功能,省去了2个硬件乘法器。这种方法能够有效地提高信号处理效率,减小硬件实现的代价,通过仿真证明了该方法的有效性和高效性。最终实现的下变频模块可以工作在200MHz的系统时钟之下,占用FPGA资源约9％。     

基于FPGA的无线移动通信系统多普勒补偿算法

利用FPGA对一种移动无线通信系统中的多普勒补偿算法进行了实现与验证。首先,对这种基于正交频分复用(OFDM)帧结构的多普勒补偿算法进行了简要介绍,该算法具有计算复杂度低、延时小、便于硬件实现的特点;然后,详细说明了该算法在实际硬件实现中各个模块的逻辑结构和工作流程;最后,将本文所实现的多普勒补偿算法模块应用到了实际的OFDM接收机中,通过硬件测试对算法和硬件实现的有效性进行了验证,并分析了算法的资源开销以及相比原算法的性能增益。     

基于FPGA的流水线CORDIC算法的DDFS设计

在射频系统后端信号处理调制解调系统中,直接数字频率合成器(DDFS)起着非常重要的作用。介绍了CORDIC算法的基本原理,提出了一种利用流水线结构生成高频率分辨率、高动态范围正弦波的方法,并给出了利用FPGA实现该流水线结构CORDIC算法的过程。     

A scaled DCT architecture with the CORDIC algorithm

This paper presents an efficient approach for computing the N-point (N=2ⁿ) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture     

An FPGA implementation of HW/SW codesign architecture for H.263 video coding

In this paper, we present an efficient HW/SW codesign architecture for H.263 video encoder and its FPGA implementation. Each module of the encoder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portions include the Discrete Cosine Transform (DCT), inverse DCT (IDCT), quantization (Q) and inverse quantization (IQ). Remaining parts were realized in software executed by the NIOS II softcore processor. This paper also introduces efficient design methods for HW and SW modules. In hardware, an efficient architecture for the 2-D DCT/IDCT is suggested to reduce the chip size. A NIOS II Custom instruction logic is used to implement Q/IQ. Software optimization technique is also explored by using the fast block-matching algorithm for motion estimation (ME). The whole design is described in VHDL language, verified in simulations and implemented in Stratix II EP2S60 FPGA. Finally, the encoder has been tested on the Altera NIOS II development board and can work up to 120 MHz. Implementation results show that when HW/SW codesign is used, a 15.8-16.5 times improvement in coding speed is obtained compared to the software based solution.