A wafer level monitoring method for plasma-charging damage usingantenna PMOSFET test structure

A novel monitoring method for plasma-charging damage is proposed. This method performs a quick and accurate evaluation using antenna PMOSFET. It was found that not only hot-carrier (HC) lifetime but transistor parameters such as initial gate current and substrate current were changed according to the degree of plasma-charging damage. However, the present work suggests that monitoring the shift of drain current after a few seconds of HC stress is a more accurate method to indicate plasma-charging damage. The monitoring method using the present test structure is demonstrated to be useful for realizing highly reliable devices     

The impact of plasma-charging damage on the RF performance ofdeep-submicron MOSFET

Integration of RF analog functions with CMOS digital circuits offers great advantages in terms of cost and performance. Plasma-charging damage is known to degrade MOSFET characteristics and can be expected to impact the RF performance as well. In this work, we present for the first time a thorough investigation of the impact of plasma-charging damage on the RF characteristics of deep-submicron MOSFET. Our result shows that, with ultra-thin gate oxide, a 400°C forming gas annealing can completely recover the RF performance degradation due to plasma-charging damage     

Plasma-charging damage in ultra-thin gate oxide

The impact of plasma-charging damage on ultra-thin gate oxide is discussed. The argument for plasma-charging damage becoming less important is examined. Without considering the area and failure rate scaling effect, one mode of charging damage does become less important while other modes continue to be a serious problem. After scaling is properly accounted for, all charging damage remains a serious problem. The problem is more serious for thinner gate oxides because its life time becomes a limiting factor in device scaling. No one has yet made proper measurement for charging damage in the ultra-thin gate oxide regime. Stress-induced leakage current with properly designed tester may be used for ultra-thin gate-oxide damage measurement if one has the required sensitivity in the measurement. However, one must take care to use stress to reveal the latent defects that are hidden by annealing.     

A simple wafer-level measurement technique for predicting oxidereliability

A new wafer-level measurement technique, the differential gate antenna analysis, has been developed to detect weaknesses in sub-micrometer oxide. This simple technique involves the use of dual antenna structures with different gate oxide areas but the same antenna area ratio. The critical parameter is the difference in their failure levels. It is shown that such a differential measurement of antenna failures correlates with product failure during accelerated life testing. The differential antenna structures are thus proven useful for real-time wafer-level monitoring of oxide reliability     

Development of the self-aligned titanium silicide process for VLSI applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-µm gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, linewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

深亚微米设计中天线效应的消除

分析了 PAE效应 (process antenna effect)的成因 ,并在此基础上提出了几种在深亚微米 ASIC设计中消除PAE效应的方法 .其方法应用于“龙芯 - I CPU”的后端设计 ,保证了投片的一次成功     

Development of the Self-Aligned Titanium Silicide Process for VLSI Applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Omega/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-/spl mu/m gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, Iinewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

Discharge-path-based antenna effect detection and fixing for X-architecture clock tree

Antenna effect is a phenomenon in the plasma-based nanometer process and directly influences the manufacturing yield of VLSI circuits. Because antenna-critical metal wires have sufficient charges to damage the thin gate oxides of the clock input ports connected by a clock tree, the standard cells or IPs cannot be driven by the clock source synchronously. For a given X-architecture clock tree that connects n clock sinks, we consider the antenna effect in the clock tree and propose a discharge-path-based antenna effect detection method. To fix the antenna violations, we use the jumper insertion technique recommended by foundries. Furthermore, we integrate the layer assignment technique to reduce the inserted jumper and via counts. Differing from the existing works, the delay of vias is considered in delay calculation, and a wire sizing technique is applied for clock skew compensation after fixing the antenna violations. Experimental results on benchmarks show that our algorithm runs in O(n²) to averagely insert 48.21% less jumpers and reduce 20.35% in vias compared with other previous algorithms. Moreover, the SPICE simulation further verifies the correctness of the resulting clock tree.     

Design of wireless on-wafer submicron characterization system

A wireless technique for the testing of very large scale ICs and wafers is presented. This test technique uses standard CMOS to achieve wireless parametric testing. This technique has virtually no area overhead, minimal power requirements, and no process or design changes are required. Most compelling is that wafer contact is not required, thereby enabling the in-line process control/monitoring of the manufacture of VLSI wafers or chips. Simulations of representative VLSI antenna designs are presented along with experimental results from the implementation of the antenna coupling and communications link. Also presented are specific circuit simulations showing the characteristics of operation under a range of conditions. The technique is demonstrated experimentally in discrete form with operation at voltages as low as 1 V with submilliwatt power levels. This technique can be implemented with a requirement of 1/10 000th the area of a Pentium-class VLSI circuit, allowing contactless testing of wafers before packaging     

Multiple-terminal gate charging effect - competing/compensating charging behavior

The charging effect from the antenna at the multiple nodes of MOSFET devices was investigated using bulk-CMOS technology. We demonstrated experimentally that the antenna size at source and drain terminals can modulate gate charging behavior, just like that at the gate terminal. However, gate charging damage is lessened when the source and/or drain antenna size increases, which is an effect opposite to that of the gate antenna. The effect can be explained by a multiple-terminal gate charging model, revealing the competing and compensating nature of the incoming charging current among the gate, source, and drain terminal of the MOSFET. The model also indicates a similar effect for the N-well antenna in P MOSFETs. The finding here leads to an application that actually utilizes metal antennae to protect gate oxide in realistic circuits.     

Quadruply self-aligned MOS (QSA MOS)—A new short-channel high-speed high-density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually self-aligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for high conductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F × 2F cell (6 µm²/cell, namely 3 × 2 mm²/1 Mbit in 1-µm rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)     

Optimized ESD protection circuits for high-speed MOS/VLSI

New electrostatic discharge (ESD) protection circuits for MOPS/VLSI provide typical 2.7-ns delays and protection against voltage spikes up to 2200 V (limit of test circuit) in some cases. These circuits contain some traditional elements plus new features including a gate-drain connected thin-oxide device to achieve the very low protected node voltage (~2 V) required for advanced thin gate oxide technologies. In addition, for CMOS application, these all-NMOS (or PMOS) circuits would offer a high degree of latchup immunity. For both positive and negative spikes, single-pulse and repeated-pulse test data were obtained for six different test conditions. Electrical and physical analyses show dominant failure modes. Because techniques used to improve protection tend to degrade speed, a figure of merit is proposed to assist a fair comparison between different ESD protection circuit designs.     

Damage to n-MOSFETs from electrical stress Relationship to processing damage and impact on device reliability

The study reported herein examines and compares damage to n-channel and p-channel metal-oxide-silicon field-effect transistors (MOSFETs) from direct current (d.c.) and alternating current (a.c.) electrical stresses as well as the relationship of this damage to plasma processing damage in MOSFETs. The lightly-doped drain (LDD) MOSFETs used are of 0.5 μm channel length and with a 90 Å thick thermally grown gate oxide fabricated using a full flow CMOS process up to and including metal-1 processes and post-metallization annealing (PMA). The damage to MOSFETs is assessed using transistor parameter characterization and charge-to-breakdown measurements on the gate oxide. It is found that manifestations of d.c. stress-induced damage and a.c. stress-induced damage to transistors are fairly similar in that both forms of damage are passivated by PMA and are reactivated by a subsequent d.c. electrical stress. However, a.c. stress-induced damage is observed to occur at much lower electric fields across the gate oxide than those necessary for d.c. stress-induced damage to be significant. This is attributed to a.c. currents, caused by carrier hopping, occurring at relatively low electric fields. One implication of our results is that plasma-charging damage, often attributed to d.c. electrical stress alone, may comprise an a.c. electrical stress component too.     

Petri net modeling of gate and interconnect delays for power estimation

Switching activity estimation is an important step in average power estimation of VLSI circuits at the gate level. In this paper, we present a novel approach based on Petri net modeling for real delay switching activity and power estimation of CMOS circuits, considering both gate and interconnect delays. We propose a new type of Petri net called hierarchical colored hardware Petri net (HCHPN), which accurately captures the spatial and temporal correlations in modeling switching activity. The logic circuit is first modeled as a gate signal graph (GSG) which is then converted into the corresponding HCHPN and simulated as a Petri net to obtain the switching activity estimates and the power values. The proposed method is accurate and fast compared to other simulative methods. Experimental results are provided for ISCAS '85 and ISCAS '89 benchmark circuits and compared with the commercial tools, PowerMill, and Prime Power.     

薄栅氧化层的TDDB研究

随着超大规模集成电路的不断发展,薄栅氧化层的质量对器件和电路可靠性的作用越来越重要。经时绝缘击穿(TDDB)是评价薄栅氧化层质量的重要方法。本文重点介绍了TDDB的几种主要击穿模型和机理,比较了软击穿和硬击穿过程的联系与区别,并初步分析了TDDB与测试电场、温度以及氧化层厚度的关系。     

薄棚氧化层的TDDB研究

随着超大规模集成电路的不断发展,薄栅氧化层的质量对器件和电路可靠性的作用越来越重要.经时绝缘击穿(TDDB)是评价薄栅氧化层质量的重要方法.本文重点介绍了TDDB的几种主要击穿模型和机理,比较了软击穿和硬击穿过程的联系与区别,并初步分析了TDDB与测试电场、温度以及氧化层厚度的关系.     

Quadruply Self-Aligned MOS (QSA MOS) -- A New Short-Channel High-Speed High-Density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually selfaligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for highconductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F X 2F cell (6 /spl mu/m/sup 2//cell, namely 3 X 2 mm/sup 2//1 Mbit in 1-/spl mu/m rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)     

Hole trap generation in the gate oxide due to plasma-inducedcharging

The paper presents results of hole trapping studies in-thin gate oxide of plasma damaged MOS transistors. Process-induced damage was investigated with antenna test structures to enhance the effect of plasma charging. In addition to neutral electron traps and passivated interface damage, which are commonly observed plasma charging latent damage, we observed and identified hole traps, generated by plasma stress. The amount of hole traps increases with increasing antenna ratio, indicating that the mechanism of hole trap generation is based on electrical stress and current flow, forced through the oxide during plasma etching. The density of hole traps in the most damaged devices was found to be larger than that in reference, undamaged devices by about 100%     

Threshold voltage shift due to low energy electrons used in SEM voltage contrast testing

Scanning electron microscope (SEM) voltage contrast testing is being developed for functional design verification, failure analysis, and development of VLSI devices. This technique imparts little electrical loading and requires no physical contact to the chip, both of which are advantages for device testing via internal nodes. One area of concern, however, is the effect of the low-energy electrons (<5 keV) on the transistor parameters. Even for incident electrons below 8 keV which do not penetrate to the gate oxide, a threshold shift has been observed in SOS MOSFET's. The parameter shift is a result of damage to the gate oxide by secondary X-rays generated by the electrons. Limits on the electron energy and fluence are set to minimize the threshold shift during SEM testing. It is found that under the proper conditions sufficient time is available to perform both voltage contrast imaging and nodal waveform measurements without incurring serious threshold voltage shifts.     

电迁移物理模型参数统计特性提取新方法

随着ＶＬＳＩ技术的发展，电迁移已成为集成电路最主要的失效原因之一，其可靠性评估技术也显得愈加重要。要改进该技术，不仅需要确定可靠性物理模型参数，而且要求掌握参数的统计分布特性。基于电迁移物理模型，提出一种提取参数统计分布特性的新方法。与传统方法相比，此方法不仅所需实验样品少、实验次数少，能真正得到反映样品离散性的物理模型参数的统计分布特性，而且也可用于其它失效机理（如栅氧击穿）物理模型中。