Field-programmable smart-pixel arrays: design, VLSI implementation, and applications

A smart-pixel array is a two-dimensional array of optoelectronic devices that combine optical inputs and outputs with electronic processing circuitry. A field-programmable smart-pixel array (FP-SPA) is a smart-pixel array capable of having its electronic functionality dynamically programmed in the field. Such devices could be used in a diverse range of applications, including optical switching, optical digital signal processing, and optical image processing. We describe the design, VLSI implementation, and applications of a first-generation FP-SPA implemented with the 0.8-microm complementary metal-oxide semiconductor-self-electro-optic effect device technology made available through the Lucent Technologies-Advanced Research Projects Agency Cooperative (Lucent/ARPA/COOP) program. We report spice simulations and experimental results of two sample applications: In the first application, we configure this FP-SPA as an array of free-space optical binary switches that can be used in optical multistage networks. In the second, we configure the device as an optoelectronic transceiver for a dynamically reconfigurable free-space intelligent optical backplane called the hyperplane. We also describe the testing setup and the electrical and the optical tests that demonstrate the correct functionality of the fabricated device. Such devices have the potential to reduce significantly the need for custom design and fabrication of application-specific optoelectronic devices in the same manner that field-programmable gate arrays have largely eliminated the need for custom design and fabrication of application-specific gate arrays, except in the most demanding applications.     

Design of an optical interconnect for photonic backplane applications

A compact alignment-tolerant interconnect has been developed for use within a prototype modulator-based free-space photonic backplane. The interconnect design encompasses several unique features. Microlens arrays are used, and several beams share each microlens by clustering the optical input-output in a small field about the optical axis of each lens. For simplifying the layout, the optical input and output of each smart-pixel array are clustered separately, thereby allowing a Fourier plane patterned-mirror array to be used in the beam-combination optics. This allows a suitable balance between high interconnection densities and reasonable optical relay distances between adjacent boards to be achieved. The primary advantages of this scheme are the simplicity of the optical design and its alignability, making it ideally suited for high-density interconnection applications.     

Optical smart-pixel-based Clos crossbar switch

We present the design of an optically interconnected Clos crossbar switch that uses three smart-pixel devices. This optical Clos architecture is also well matched to a space-wavelength switch that arbitrarily permutes data streams between wavelength-division multiplexed channels on an array of fibers. We have designed a hybrid complementary metal-oxide semiconductor-self-electro-optic device (CMOS-SEED) crossbar smart-pixel array for use in a 16-channel optical Clos switch. The crossbar devices also have an 8 x 8 array of multiple-quantum-well diodes that can be configured electrically as modulators with eight bit planes of randomly addressable local memory or as receivers with adjustable gain and threshold. We show that the current hybrid-SEED technology should support a 1024-channel Clos switch operating at 500 Mbits/s per channel if pixel power consumption can be reduced.     

Optoelectronic parallel-matching architecture: architecture description, performance estimation, and prototype demonstration

We propose an optoelectronic parallel-matching architecture (PMA) that provides powerful processing capabilities in global processing compared with conventional parallel-computing architectures. The PMA is composed of a global processor called a parallel-matching (PM) module and multiple processing elements (PE's). The PM module is implemented by a large-fan-out free-space optical interconnection and a PM smart-pixel array (PM-SPA). In the proposed architecture, by means of the PM module each PE can monitor the other PE's by use of several kinds of global data matching as well as interprocessor communication. Theoretical evaluation of the performance shows that the proposed PMA provides tremendous improvement in global processing. A prototype demonstrator of the PM module is constructed on the basis of state-of-the-art optoelectronic devices and a diffractive optical element. The prototype is assumed for use in a multiple-processor system composed of 4 x 4 PE's that are completely connected through bit-serial optical communication channels. The PM-SPA is emulated by a complex programmable device and a complementary metal-oxide semiconductor photodetector array. On the prototype demonstrator the fundamental operations of the PM module were verified at 15 MHz.     

Perfect-shuffle interconnected bitonic sorter: optoelectronic design

The algorithmic, electronic, and optical aspects of the implementation of a perfect-shuffle interconnected bitonic sorter are analyzed. The performance metrics such as the bit output data rate and the power consumption of the system are quantified. The sorting module is designed to demonstrate the parallel nonlocal interconnection of smart-pixel arrays and the use of optical-image control masks in a functioning information processor.     

Time multiplexing and control for optical cellular-hypercube arrays

We discuss the cellular-hypercube optical free-space interconnection architecture and its implementation by two-dimensional smart-pixel optoelectronic cellular arrays. We emphasize the behavior of the cellular hypercube in performing shift-invariant parallel shifts of data, a basic requirement of most single-instruction multiple-data algorithms. We present a time-multiplexing scheme for realizing the cellular hypercube, showing that the communication time is inversely proportional to the number of optical detectors per cell. We also present an improved hybrid interconnection network with improved performance that combines the cellular hypercube and mesh, using optics for the longer-distance connections and electronics for nearest-neighbor connections.     

Demonstration and architectural analysis of complementary metal-oxide semiconductor /multiple-quantum-well smart-pixel array cellular logic processors for single-instruction multiple-data parallel-pipeline processing

We present an optoelectronic-VLSI system that integrates complementary metal-oxide semiconductor/multiple-quantum-well smart pixels for high-throughput computation and signal processing. The system uses 5 x 10 cellular smart-pixel arrays with intrachip electrical mesh interconnections and interchip optical point-to-point interconnections. Each smart pixel is a fine grain microprocessor that executes binary image algebra instructions. There is one dual-rail optical modulator output and one dual-rail optical detector input in each pixel. These optical input-output arrays provide chip-to-chip optical interconnects. Cascading these smart-pixel array chips permits direct transfer of two-dimensional data or images in parallel. We present laboratory demonstrations of the system for digital image edge detection and digital video motion estimation. We also analyze the performance of the system compared with that of conventional single-instruction-multiple-data processors.     

Optoelectronic-cache memory system architecture

We present an investigation of the architecture of an optoelectronic cache that can integrate terabit optical memories with the electronic caches associated with high-performance uniprocessors and multiprocessors. The use of optoelectronic-cache memories enables these terabit technologies to provide transparently low-latency secondary memory with frame sizes comparable with disk pages but with latencies that approach those of electronic secondary-cache memories. This enables the implementation of terabit memories with effective access times comparable with the cycle times of current microprocessors. The cache design is based on the use of a smart-pixel array and combines parallel free-space optical input-output to-and-from optical memory with conventional electronic communication to the processor caches. This cache and the optical memory system to which it will interface provide a large random-access memory space that has a lower overall latency than that of magnetic disks and disk arrays. In addition, as a consequence of the high-bandwidth parallel input-output capabilities of optical memories, fault service times for the optoelectronic cache are substantially less than those currently achievable with any rotational media.     

Hybrid free-space optical bus system for board-to-board interconnections

A free-space optical bus system is described for board-to-board interconnections at the backplane level. The system uses active optoelectronic modules as the interface between the circuit boards and the electrical backplane. Substrate-mode holograms are used to implement signal broadcast operations between boards, and each board on the backplane shares common free-space channels for transmitting and receiving signals. System-design considerations are given, and the potential performance of the optical bus system is evaluated. An experimental demonstration is also presented for the signal broadcast operation through cascaded substrate-mode holograms at a data rate of 622 Mb/s.     

Design, implementation, and characterization of an optical power supply spot-array generator for a four-stage free-space optical backplane

The design and implementation of a robust, scalable, and modular optical power supply spot-array generator for a modulator-based free-space optical backplane demonstrator is presented. Four arrays of 8 x 4 spots with 6.47-mum radii (at 1/e(2) points) pitched at 125 mum in the vertical direction and 250 mum in the horizontal were required to provide the light for the optical interconnect. Tight system tolerances demanded careful optical design, robust optomechanics, and effective alignment techniques. Issues such as spot-array generation, polarization, power efficiency, and power uniformity are discussed. Characterization results are presented.     

Optical encryption of digital data

Smart-pixel architectures, which use the cells of field-programmable gate arrays to provide electronic functionality and intraplane communication, offer a general-purpose approach to exploiting new application areas that would benefit from this kind of structure. One such area, that of the encryption of digital data, is discussed here. Some of the characteristics exhibited by encryption algorithms and ways in which these are applicable to smart-pixel technology are described. The implementation of an algorithm in current use, the SAFER K-64, and its interfacing to an electronic host are then considered in detail. It is shown that this encryption algorithm maps well onto smart-pixel technology because it involves only parallel data transfers, simple regular operations, and interconnections plus a relatively low rate of transfer to the host.     

Analysis of a microchannel interconnect based on the clustering of smart-pixel-device windows

A design analysis of a telecentric microchannel relay system developed for use with a smart-pixel-based photonic backplane is presented. The interconnect uses a clustered-window geometry in which optoelectronic device windows are grouped together about the axis of each microchannel. A Gaussian-beam propagation model is used to analyze the trade-off between window size, window density, transistor count per smart pixel, and lenslet ?-number for three cases of window clustering. The results of this analysis show that, with this approach, a window density of 4000 windows/cm(2) is obtained for a window size of 30 μm and a device plane separation of 25 mm. In addition, an optical power model is developed to determine the nominal power requirements of a 32 × 32 smart-pixel array as a function of window size. The power requirements are obtained assuming a complementary metal-oxide semiconductor inverter-amplifier and dual-rail multiple-quantum-well self-electro-optic-effect devices as the receiver stage of the smart pixel.     

Design and characterization of a microchannel optical interconnect for optical backplanes

The design, modeling, and experimental characterization of a microchannel-based free-space optical interconnect is described. The microchannel interconnect was used to implement a representative portion of an optical backplane that was based on field-effect transistor, self-electro-optic device smart-pixel transceivers. Telecentric relays were used to form the optical interconnect, and two modes based on two different optical window clusterings were implemented. The optical system design, including the optical geometry for different degrees of clustering of windows supported by a lenslet relay and the image mapping associated with a free-space optical system, is described. A comparison of the optical beam properties at the device planes, including the spot size and power uniformity of the spot array, as well as the effects of clipping and misalignment for the different operating modes, is presented. In addition, the effects of beam clipping and misalignment for the different operating modes is presented. We show that microchannel free-space optical interconnects based on a window-clustering scheme significantly increase the connection density. A connection density of 2222 connections/cm(2) was achieved for this prototype system with 2 x 2 window clustering.     

Analysis of a hybrid micro/macro-optical method for distortion removal in free-space optical interconnections

Eikonal analyses are applied to a hybrid micro/macro-optical shuffle interconnection approach that minimizes distortion in a multichip smart-pixel shuffle interconnection system. The optical system uses off-axis imaging elements to link clusters of dense arrays of vertical-cavity surface-emitting laser (VCSEL) sources to matching clusters within arrays of detectors. A critical requirement for such a system is that the images of the two-dimensional arrays of the VCSELs must be registered on their associated detector arrays with a precision of the order of 10 microm across the entire multichip array. The hybrid approach exploits the typical narrow-beam cone angles of VCSELs by use of beam-deflecting micro-optics to create a distortion-canceling symmetry about a central aperture in the optical system for each VCSEL-detector link. The second- and third-order aberrations of the plane-symmetric system created by the global off-axis imaging system are analyzed. The results prove that the hybrid concept cancels distortion and minimizes the spot size at the detector array plane.     

Performance evaluation of massively parallel processing architectures with three-dimensional optical interconnections

We evaluate the performance of three-dimensional optoelectronic computer architectures on the basis of basic database operations and parallel benchmark algorithms for numerical computations. We show that the select and the join database operations can be performed much faster with an optical interconnection network. Also, optoelectronic architectures can perform the fast Fourier transform and sorting benchmarks orders of magnitude faster than electronic supercomputers. An architecture with an adequately fast reconfigurable interconnection network can perform the conjugate-gradient benchmark faster than all parallel supercomputers, but its performance is not as impressive when a fixed network is used. In the case of the multigrid benchmark the three-dimensional optoelectronic architecture also can outperform the best parallel supercomputers.     

Performance analysis of self-electro-optic-effect-device-based (SEED-based) smart-pixel arrays used in data sorting

The performance factors associated with self-electro-optic-effect-device-(SEED-) based smart-pixel arrays are analyzed in terms of semiconductor technology and pixel complexity. The sorting task is chosen as a practical example. Complementary metal-oxide semiconductor (CMOS)-SEED 2 × 2 self-routing nodes operated with quasi-cw-mode lasers are shown to provide the maximum processing power and on- or off-chip communication rate. The need for new front-end amplifiers for the smart-pixel technology is emphasized.     

Optoelectronic pipeline architecture for morphological image processing

An optoelectronic architecture for morphological image processing is presented. The architecture uses the pipelining principle, with its stages being implemented by use of optical fiber-based programmable logic arrays. These arrays are characterized by their high fan-in and fan-out factors, which make them suitable for implementing morphological operations with large structuring elements without decomposition. The pipeline has fewer stages and clock skew can be avoided, thus making the use of higher clock speeds and throughputs possible.     

Node-based reconfigurable volume interconnections. 1. Principles and optical design

We present a general-purpose three-dimensional interconnection network that models various parallel operations between two data planes. This volume interconnection system exhibits reconfigurable capabilities because of parallel and externally weighted interconnection modules, called nodes. We propose a generic optical implementation based on the cascading of two planar hologram arrays, coupled with a bistable optically addressed spatial light modulator. The role of this component is discussed in terms of energy regeneration and spatial cross-talk limitation. As an example, a binary matrix-matrix multiplier is implemented that uses a ferroelectric liquid-crystal light valve.     

Locality and decomposition of regular optical interconnection patterns

Methods that a designer can use to optimize the placement of nodes in a large switching network to decrease the requirements on holographic interconnections are investigated. Localized interconnections between subdivided switches are combined with simpler global interconnections. The interconnections between subdivided switches can be implemented by use of metallic traces on smart-pixel arrays. The global interconnections would be provided by optical free-space techniques. Several advantages arise from this procedure: (1) The regular interconnection pattern is decomposed into several pipes (collection of light beams that form a complete pattern) without loss of functionality. (2) The interconnection pattern may be optimized by variation of the placement of the switches in a switching network (e.g., to obtain a minimum deflection angle). (3) The interconnection pattern may be adjusted to the need of an algorithm by an additional parameter (the dimension). The application to photonic switching networks and signal processing is discussed.     

Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability

We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96.04 mm(2) chip using an 0.35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21 μs partial reconfiguration.