Design consideration of p-well structure for solid-state image sensors

The p-well structure has been widely used in solid-state image sensors to suppress blooming and smear. This structure, however, suffers from saturation-level shading, flicker, and saturation-level fixed pattern noise. This work clarifies that the p-well potential sway, due to transfer pulse feeding, brings about the shading and the flicker, and the impurity fluctuation in the silicon substrate causes the saturation-level fixed pattern noise. To eliminate the problems, new structures and new driving modes are proposed. As a result, the shading is reduced to a practically negligible level, and the flicker and the fixed pattern noise are completely suppressed.     

增强型CCD图像传感器

扩展ＣＣＤ有用成像和探测范围的工作已进行，该工作是通过直接光学耦合和像增强器与ＣＣＤ组合来实现，已经证明，采用现有国产ＣＣＤ和微通道板像增强耦合技术可提高ＣＣＤ有用的范围２个数量级。     

Photo response analysis in CCD image sensors with a VOD structure

Photo response in CCD image sensors with Vertical-Overflow-Drain (VOD) was analyzed in an attempt to discover a way to lessen the photo response rise that accompanies increasing incident light intensity in the saturation region. A photo response analysis based on transistor I-V characteristics revealed that the extent of rise in the saturation region is uniquely determined by the non-ideality factor and temperature. Calculation of the non-ideality factor and its dependence on P-well impurity concentration and layer thickness further revealed that fabrication of P-wells with lower impurity concentrations and thicker layers would be effective in suppressing photo response rise     

High-resolution CCD image sensors with reduced smear

Two types of interline transfer CCD image sensors with reduced smear signal were developed, one for a 525-line TV system (EIA) and one for a 625-line system (CCIR). An MOS diode is employed as a sensing element to realize negligibly small lag compared with that of a junction diode. The EIA and CCIR version have effective number of pixels of 510 × 492 and 500 × 582, respectively. Smear is reduced down to -92 dB by fabricating the vertical shift register on the p-well. In spite of the shrunken element area, the blue sensitivity similar to that for a conventional 384 × 491 CCD imager [1] is obtained by optimization of the film thickness on the diode. Resolution as high as 330 TV lines in color is also attained.     

CCD图像传感器的微透镜阵列设计与实验研究

为了最大程度地改善CCD图像传感器的填充因子,进行了用于与CCD集成的微透镜阵列的光学优化设计,并与实验结果进行了对比。测试结果表明,所设计的透镜阵列使CCD的填充因子提高2.9倍,相对光谱响应增加了0.2。所设计的透镜对于改善CCD入射信号光的光强分布、提高光利用效率,从而提高CCD的光电性能有显著效果。     

UV-responsive CCD image sensors with enhanced inorganic phosphor coatings

Typical polysilicon gate charge-coupled device (CCD) image sensors are unresponsive to ultraviolet (UV) light because of the high absorption of the radiation in polysilicon gate material, which leads to a short penetration depth (<2 nm), and absorption of the radiation in the gate material rather than within the channel of the CCD. An inorganic phosphor coating to convert the UV radiation to visible has been developed. Although the coating is similar to acrylics doped with organic laser dyes reported previously, in this work the organic dye has been replaced with a more robust inorganic phosphor. In addition, a new deposition method has been developed to improve the photoresponse nonuniformity (PRNU) of the coated sensor. The inorganic phosphor has been selected over organic laser dyes because organic molecules degrade rapidly upon exposure to UV radiation, with exponential degradation rates as high as 3% per hour at an illumination level of 1 /spl mu/W/cm/sup 2/. Inorganic phosphors exhibit reduced degradation with 90% of the degradation occurring within the first 2% of the material's lifetime. It is this stabilization that improves the viability of phosphor-coated CCD image sensors for commercial applications. The quantum efficiency observed was 12% at 265 nm. The improved deposition technique reduced the photoresponse nonuniformity degradation fourfold, so the observed PRNU was only 0.4 times greater than that of the uncoated sensor.     

Latchup suppression in fine-dimension shallow p-well CMOS circuits

The high packing density required for VLSI CMOS circuits leads to enhanced performance of the inherent parasitic bipolar devices, and thus latchup becomes a major problem. One of the most attractive techniques for overcoming this is to fabricate the devices on n-on-n⁺epitaxial substrate material. This paper deals with latchup suppression by such a technique in fine-dimension CMOS circuits based on very shallow p-wells. Experimental results demonstrate that latchup may be eliminated in structures with p-well depths as shallow as 0.8 µm at supply voltages up to 10 V and temperatures up to 140°C. Furthermore, this may be achieved with no significant degradation of other aspects of device or circuit performance. A simple lumped model equivalent circuit has been used to predict latchup characteristics where appropriate, and in general this gives good agreement with experiment.     

Technologies to improve photo-sensitivity and reduce VOD shuttervoltage for CCD image sensors

New technologies to increase the photo-sensitivity and reduce the shutter voltage of the vertical over-flow-drain (VOD) have been developed for CCD image sensors. The photo-sensitivity was increased 40% by forming an anti-reflection film over the photodiode and reducing the thickness of the p⁺-layer formed at the photodiode surface. The VOD shutter voltage was reduced from 31 to 18 V by using an epitaxially grown substrate with double impurity concentration layers     

Theoretical analysis and optimization of CDS signal processingmethod for CCD image sensors

The correlated double sampling (CDS) signal processing method used in processing of video signals from CCD image sensors is theoretically analyzed. The CDS signal processing is frequency used to remove noise, which is generated by the reset operation of the floating diffusion charge detection node, from the signal. The derived formulas for the noise power spectral density provide an invaluable insight into the choice of the circuit parameters affecting the noise spectrum. The obtained results are useful for determining the optimum cutoff frequency of the low-pass filter which precedes the sample-and-hold circuit and for finding the optimum size of the input transistor in the first amplifier stage. Once the optimum parameters are determined it is possible to find the minimum electron equivalent noise and the maximum signal-to-noise ratio achievable with this signal processing method. The validity of the derived theoretical results is confirmed by making comparisons with the experimental data     

BCMD-An improved photosite structure for high-density image sensors

The author describes a new improved photosite structure and its use in a new image sensor that has been developed for applications requiring high-density pixel integration. The new photosite employs a buried-channel MOS transistor with a specially designed storage well located under the transistor channel in the silicon bulk. The photogenerated carriers accumulate in this well and modulate the transistor threshold. The resulting bulk charge modulated device (BCMD) has a high-sensitivity low-noise high-blooming overload capability, no detectable smear, and no image lag. The BMCD photocell has been integrated into an image-sensing array that has an 8-mm diagonal, 499 lines, and 687 pixels in each line. The individual cells are shaped into closely packed hexagons and are offset by a half pixel width between the neighbouring lines. The half pixel offset together with the dual-time readout capability gives the new sensor its superior resolution in color-sensing applications. The high light sensitivity throughout the entire visible spectrum is achieved by using a very thin polysilicon gate. The peripheral circuits needed for the array addressing and sensing functions are integrated on-chip using CMOS technology and require only the TTL driving pulses. The author further describes the basic steps of the sensor fabrication process and the results of testing and evaluation of completed units     

提高CCD图像传感器填充因子的微透镜阵列的研究

为了提高可见光CCD图像传感器的探测灵敏度,提出了516×516元石英微透镜阵列的设计方法,并简要介绍了其制作工艺.测量结果表明,所制作的微透镜阵列有优良的表面轮廓、较好的几何尺寸均匀性和光学性能,大幅度地提高了CCD图像传感器的填充因子.     

Interline CCD image sensor with an antiblooming structure

A ⅔-in 384 (H) × 490 (V) element interline CCD image sensor with a new antiblooming structure was developed. Blooming was suppressed without sacrificing photosensitivity and dynamic range by means of a vertical overflow drain positioned under (rather than beside) a photodiode. For 10-percent vertical height illumination the smear signal was reduced to 0.05 percent of the illumination signal. Well-balanced performance, namely, large dynamic range (72 dB), low random noise (65 rms noise electrons per charge packet), high-contrast transfer functions for horizontal and vertical directions, and a spectral response similar to the luminous efficiency curve were obtained under moderate operating conditions.     

A CCD image preprocessor for Hadamard transform operations

A simple preprocessor structure is presented that uses external ROM or microprocessor control to implement the Hadamard transform efficiently in CCD devices.     

A retrograde p-well for higher density CMOS

A new technique for CMOS p-well (or n-well) formation is described, making use of a deep implant followed by a brief anneal. This results in a retrograde profile, permitting a much shallower well, a large reduction in p-n channel device spacing (5-6 µm versus 10-15 µm), and an opportunity to reduce the risk of latch-up. This technique is more conducive to scaling-with the promise of significantly better performance-than conventional well formation methods. The retrograde p-well has been successfully applied to a linearly shrunk bulk CMOS 4K static RAM, demonstrating its feasibility.     

CCD linear image sensor with buried overflow drain structure

A CCD linear image sensor with buried overflow drain structure has been developed. Since the overflow drain, i.e. a reverse biased n-region buried under photosites arrayed in p-layer, makes an effective sink of excess electrons, imaging characteristics such as uniformity of photosensitivity, spectral response, resolution, and antiblooming, are highly improved.     

A Nyquist-rate pixel-level ADC for CMOS image sensors

A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADCs can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320×256 sensor using the MCBS ADC is described. The chip measures 4.14×5.16 mm². It achieves 10×10 μm² pixel size at 28% fill factor in 0.35 μm CMOS technology. Each 2×2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively     

A low driving voltage CCD with single layer electrode structure forarea image sensor

A new single layer electrode two-phase CCD was studied for the purpose of realizing low driving voltage operation in inter-line transfer CCD (IT-CCD) image sensor aiming for low power consumption. Conventional H-CCD with overlapping double layer electrode structure have not achieved signal charge transfer at very low driving voltage below 2 V due to appearance of potential pocket under the inter-electrode gap yet. The new CCD employs a new channel doping profile for potential pocket suppression at the inter-electrode gap. The new CCD also employs a stepped-oxide structure having a single layer transfer electrode covering both a thin gate oxide forming storage region and a thinner gate oxide forming barrier region. The inter-electrode gap of single layer electrode was decreased to as small as 0.3 μm. As a result of these measures, a fabricated 1/3 in format 270 K pixel IT-CCD image sensor reproduces a fine video image even when it is operated at a driving voltage as low as 1.8 V     

The effects of smear on antiblooming protection and dynamic rangeof interline CCD image sensors

The effects of a smearing signal on the dynamic range and the amount of antiblooming protection of an interline CCD image sensor are presented. It is shown that there is a tradeoff between these two parameters, and that they are directly related by the amount of smear. These relationships are analyzed for both constant-integration time and constant-irradiance modes of operation. For the constant-irradiance model of operation it is shown that in order to maintain 90% of the maximum dynamic range and an antiblooming protection of 300×, the smear signal must be less than 0.037%. For the constant integration-time mode of operation, it is shown that in order to maintain 75% of a particular device's maximum dynamic range and the same amount of antiblooming protection the smear signal must be less than 0.0074%. It is also found in this mode that this relationship between antiblooming protection and the amount of linear dynamic range is exponential, and dependent on the antiblooming structure's nonideality factor and the individual photodetector's capacitance     

A 9-b charge-to-digital converter for integrated image sensors

Charge-to-digital conversion offers advantages over conventional charge readout techniques because it performs digitization directly in the charge domain. The approach consolidates hardware, reduces power and weight, and eliminates many sources of noise and nonlinearity. This paper introduces an architecture for a charge-to-digital converter (CDC) that is tailored toward a charge-coupled device (CCD) implementation. New methods of generating charge, sensing charge, and comparing charge packets are described that improve conversion accuracy. Factors limiting device performance are discussed. Measured results are presented for two prototype CDCs. The first, using buried channel CCDs, is optimized for resolution. It achieves 56 dB spurious free dynamic range (SFDR) at a 2 MHz sampling rate and operates from 5 V. The second, using surface channel CCDs, is optimized for power and speed. It achieves 49 dB SFDR at a 15 MHz sampling rate and consumes 13 mW power at its maximum sampling rate of 22 MHz