An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.     

An implantable wireless bidirectional communication microstimulator for neuromuscular stimulation

This paper presents the integrated circuit design for a wireless bidirectional transmission microstimulator. This implantable device is composed of an internal radio-frequency (RF) front-end circuit, a control circuit, a stimulator, and an on-chip transmitter. A 2-MHz amplitude-shift keying modulated signal, including the power and data necessary for the implantable device, is received, and a stable 3-V dc voltage and digital data will be extracted to further execute neuromuscular stimulation. The current-mode microstimulator can produce a bidirectional output current with 8-bit resolution for stimulation. The maximum stimulation current is 1 mA while the stimulation frequency is from 20 Hz to 2 kHz and the pulsewidth of stimulation current is from 150 to 500 /spl mu/s. Furthermore, the system can acquire the biological sensing signal by means of an on-chip transmitter. Most of the signal processing circuits have been designed with low-power schemes to reduce the power consumption, and the performance is also conformed to the requirements of the microstimulator. All of the circuits except for the RF link are combined in a single chip and implemented in TSMC 0.35-/spl mu/m 2P4M standard CMOS process.     

An 8-Gb/s simultaneous bidirectional link with on-die waveform capture

A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-/spl mu/m CMOS. This equalized transceiver has been optimized for small area (329 /spl mu/m /spl times/ 395 /spl mu/m) and low power (158 mW) for point-to-point parallel links. Source-synchronous clocking and per-pin skew compensation eliminate coding bandwidth overhead and reduce latency, jitter, and complexity. This link is self-configuring through the use of automatic comparator offset trim and adaptive deskew. Comprehensive diagnostic capabilities have been integrated into the transceiver to provide link, interconnect, and circuit characterization without the use of external test equipment. With a resolution of 4 mV and 9 ps, these capabilities enable on-die eye diagram generation, equivalent time waveform capture, noise characterization, and jitter distribution measurements.     

A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet

A 3.125-Gb/s clock and data recovery (CDR) circuit using a half-rate digital quadricorrelator frequency detector and a shifted-averaging voltage-controlled oscillator is presented for 10-Gbase-LX4 Ethernet. It can achieve low-jitter operation and improve pull-in range without a reference clock. This CDR circuit has been fabricated in a standard 0.18-/spl mu/m CMOS technology. It occupies an active area of 0.6 /spl times/ 0.8 mm/sup 2/ and consumes 83 mW from a single 1.8-V supply. The measured bit-error rate is less than 10/sup -12/ for 2/sup 7/ - 1 PRBS 3.125-Gb/s data. It can meet the jitter tolerance specifications for the 10-Gbase-LX4 Ethernet application.     

A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine

A fully digital, self-adjusting, and high-efficiency power supply system has been developed based on a finite-state machine (FSM) control scheme. The system dynamically monitors circuit performance with a delay line and provides a substantially constant minimum supply voltage for digital processors to properly operate at a given frequency. In addition, the system adjusts the supply voltage to the required minimum under different process, voltage, and temperature and load conditions. The design issues of the fully digital power delivery system are discussed and addressed. This digital FSM scheme significantly reduces the complexity of control-loop implementation (<1800 gates) and power consumption (< 100 /spl mu/W at 1.2 V) compared to other approaches based on proportional-integral-differential control. The power delivery control system is fabricated in a 0.13-/spl mu/m CMOS process and its core die size is 160 /spl times/ 110 /spl mu/m/sup 2/.     

A single-chip NMOS analog front-end LSI for modems

Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.     

An analog front end for a two-chip 2400-bit/s voice-band modem

A complete two-chip solution comprised of an analog front end (AFE) and a general-purpose microcontroller (/spl mu/C) for a full-duplex 2400-b/s modem is discussed. The /spl mu/C performs all the necessary digital signal processing algorithms for modem signals along with providing software for modem control and the widely used AT command set. The AFE chip incorporates a ROM-based transmitter, 51 orders of filtering for channel selection, an automatic pain control circuit, and many other complex analog signal processing functions employing 65 op-amps on a 53000-mil/SUP 2/ die area with 150-mW power in a CMOS process. Design details on some of the functional blocks of the AFE are presented.     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking

This paper describes a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Although minimizing the circuit area has become critical in multibit interfaces such as the SFI-5, few studies have proposed a practical method of reducing the area of data recovery circuits. We introduce a digital-PLL-type DR circuit design with eye-tracking, which we developed to minimize the circuit area and power consumption without degrading tolerance against jitter. This novel method of data recovery enabled us to simplify the circuit design against process, voltage, and temperature variations. Design considerations on how to eliminate high-frequency jitter and how to track long-term wander are described. The design for 2.5-GHz clock distribution is also discussed. The area of the DR circuit, fabricated with 0.18-/spl mu/m SiGe BiCMOS technology, is 0.02 mm/sup 2//ch, and its power consumption is 50 mW/ch at 1.8 V. The measured tolerance against jitter at 2.5 Gb/s is 0.7 UI peak-to-peak, which satisfies the jitter specifications for the SFI-5.     

A 4-/spl mu/a quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications

This paper describes a dual-mode digitally controlled buck converter IC for cellular phone applications. An architecture employing internal power management is introduced to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology. Special purpose analog and digital interface elements are developed. These include a ring-oscillator-based A/D converter (ring-ADC), which is nearly entirely synthesizable, is robust against switching noise, and has flexible resolution control, and a very low power ring-oscillator-multiplexer-based digital pulse-width modulation (PWM) generation module (ring-MUX DPWM). The chip, which includes an output power stage rated for 400 mA, occupies an active area 2 mm/sup 2/ in 0.25-/spl mu/m CMOS. Very high efficiencies are achieved over a load range of 0.1-400 mA. Measured quiescent current in PFM mode is 4 /spl mu/A.     

A true-1-V 300-/spl mu/W CMOS-subthreshold log-domain hearing-aid-on-chip

This paper presents a true very low-voltage low-power complete analog hearing-aid system-on-chip as a demonstrator of novel analog CMOS circuit techniques based on log companding processing and using MOS transistors operating in subthreshold. Low-voltage circuit implementations are given for all of the required functions including amplification and automatic gain control filtering, generation, and pulse-duration modulation. Based on these blocks, a single 1-V 300-/spl mu/A application specific integrated circuit integrating a complete hearing aid in a standard 1.2-/spl mu/m CMOS technology is presented along with exhaustive experimental data. To the authors' knowledge, the presented system is the only CMOS hearing aid with true internal operation at the battery supply voltage and with one of the lowest current consumptions reported in literature. The resulting low-voltage CMOS circuit techniques may also be applied to the design of A/D converters for digital hearing aids.     

A programmable gain/loss circuit

A general-purpose gain/loss circuit is described. Its function is controlled by an 8-b digital word. It provides up to 256 0.1-dB steps in gain or loss. The circuit has two modes of incremental gain/loss steps (two sets of gain/loss values for bits in the control word). A ninth bit selects between gain and loss. The IC has three digital interfaces: serial, parallel clocked input, and parallel fixed input. The chip is fabricated in a 3-/spl mu/m CMOS n-well process. It requires a /spl plusmn/5-V power supply, and for maximum gain of 25.5 dB, the 0.1-dB large-signal bandwidth is 260 kHz.     

A 256-element CMOS imaging receiver for free-space optical communication

This paper describes a CMOS imaging receiver for free-space optical (FSO) communication. The die contains 256 optical receive channels with -47 dBm optical sensitivity and 30 dB optical dynamic range at 500 kb/s/channel while consuming 67 mW. Received signals are amplified by digitally self-calibrated open-loop amplifiers and digitized before clock and data recovery. The sampled data also provide inputs for digital automatic gain and offset control loops closed around the analog amplifier chain to compensate for signal variations due to atmospheric turbulence and daylight interference. Gain control logic can adapt to incident signals over the 30 dB dynamic range within 28 bit periods. Low-power logic design and analog circuit techniques are used to minimize digital crosstalk to single-ended photodetectors referenced to a bulk substrate. Local arbitration circuitry at each channel forms an intrachip data passing network to multiplex received data words from the 16 /spl times/ 16 array onto a common off-chip bus. The 1.6 M transistor mixed-signal die fabricated in a 0.25 /spl mu/m CMOS process measures 6.5/spl times/6.5 mm/sup 2/. Reception at 500 kb/s through a 1.5 km atmospheric channel is demonstrated with 3 mW optical transmit power during nighttime and daylight hours.     

A low-power analog motion estimation processor for digital video coding

Analog circuit techniques can be beneficially applied to reduce the circuit complexity and power consumption of motion estimation processors for digital video encoding. However, analog circuits are sensitive to mismatch which affects motion estimation. This paper presents the design of an analog motion estimation processor which overcomes these limitations. A novel architecture is described featuring pixel reuse and input offset error cancellation. The proof-of-concept realization was fabricated in 0.8-/spl mu/m CMOS, and operates on 4/spl times/4 pixel blocks and a search area of 8/spl times/8 pixels. However, the architecture is scalable to larger block sizes and more advanced technologies. Measured results for various QCIF video sequences at 15-f/s showed excellent PSNR performance. The prototype dissipates 0.9 mW of power from a single 3-V power supply and occupies an area of 0.95 mm/sup 2/. Energy consumption is 1.51 nJ per motion vector.     

A digitally controlled constant envelope phase-shift modulator for low-power broad-band wireless applications

A low-power constant envelope phase-shift modulator is presented. The circuit switches the phase of a constant amplitude carrier at output according to the input digital data. Design issues and their impact on the performance of the modulator are discussed. A test chip was fabricated in a 0.18-/spl mu/m CMOS process. Experiment results verified the design principle of the modulator. The modulator consumes 2 mA and is suitable for low-power wireless applications like sensor network and personal area network. Since the circuit is implemented mostly by digital circuit, has broad-band frequency response, and supports high data rate, the modulator can be used at various wireless bands. The measured operating range of carrier frequency is 1.75 to 3.5 GHz, and the modulation data rate can go up to 500 Mb/s. In addition, the modulator can be modified to generate different modulations by digitally controlling both the phase and amplitude of the output signal from a phasor-combining circuit. Therefore, the modulator can potentially be used for software configurable radios.     

Development of QTAT online electronic circuit patterning system

An arbitrary pattern exposure system has been developed by employing a liquid crystal display (LCD) with 1600 /spl times/ 1200 pixels for the formation of projection images in place of a conventional reticle. The minimum pattern size becomes 11.5 /spl mu/m, which corresponds to the aperture size of each pixel on the LCD. For the purpose of quick turnaround time (TAT), the exposure system was directly connected to the circuit design system with the transmission control protocol/internet protocol network. From the experimental results on patterning of a typical electronic circuit data with the area of 46/spl times/ 46 mm, it was confirmed that the TAT from the output of design data to the finish of the exposure becomes less than 28 min. By using this system, reduction of the production cost in the printed wiring boards fabrication is expected.     

An all-digital analog-to-digital converter with 12-/spl mu/V/LSB using moving-average filtering

A compact, high-resolution analog-to-digital converter (ADC) especially for sensors is presented. The basic structure is a completely digital circuit including a ring-delay-line with delay units (DUs), along with a frequency counter, latch, and encoder. The operating principles are: (1) the delay time of the DU is modulated by the analog-to-digital (A/D) conversion voltage and (2) the delay pulse passes through a number of DUs within a sampling (= integration) time and the number of DUs through which the delay pulse passes is output as conversion data. Compact size and high resolution were realized with an ADC having a circuit area of 0.45 mm/sup 2/ (0.8-/spl mu/m CMOS) and a resolution of 12 /spl mu/V (10 kS/s). Its nonlinearity is /spl plusmn/0.1% FS per 200-mV span (1.8-2.0 V), for 14-b resolution. Sample holds are unnecessary and a low-pass filter function removes high-frequency noise simultaneously with A/D conversion. Thus, the combination of this ADC and a digital filter that follows can eliminate an analog prefilter to prevent the aliasing before A/D conversion. Also, both this ADC can be shrunk and operated at low voltages, so it is an ideal means to lower the cost and power consumption. Drift errors can be easily compensated for by digital processing.     

A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply

A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98 dB with 2 dB gain steps and is controlled by 6-bit gain control bits for a 3 V power supply. It has been fabricated in a 0.5 /spl mu/m 15 GHz f/sub T/ Si BiCMOS process and draws 13 mA. The active die area taken up by the circuit is 400 /spl mu/m /spl times/ 1170 /spl mu/m. A noise figure (NF) of 4.9 dB was measured at the maximum gain setting. In addition, an analysis of the bias current generation to provide dB-linear gain control is presented.     

A GaAs data switching IC for a gigabits per second communication system

A GaAs monolithic 4/spl times/4 switching circuit has been developed for high-speed digital communication systems. This switching IC, which has built-in address decoders, is completely ECL-compatible. Dynamic performance measurements on the chip mounted in a 32-pin flat package prove that it correctly switches pseudorandom data transmitted at more than 2 Gb/s, switching in 1 ns. The pulsewidth variation is only /spl plusmn/60 ps at 2 Gb/s. Very stable operation is observed from 0 to 70/spl deg/C ambient temperature for supply voltage fluctuations of /spl plusmn/5%.     

A low-power 22-bit incremental ADC

This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-/spl mu/m CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 /spl mu/V/sub RMS/), the DC offset 2 /spl mu/V, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 /spl mu/A current during conversion.