A low energy adaptive motion estimation hardware for H.264 multiview video coding

Multiview video coding (MVC) is the process of efficiently compressing stereo (two views) or multiview video signals. The improved compression efficiency achieved by H.264 MVC comes with a significant increase in computational complexity. Temporal prediction and inter-view prediction are the most computationally intensive parts of H.264 MVC. Therefore, in this paper, we propose novel techniques for reducing the amount of computations performed by temporal and inter-view predictions in H.264 MVC. The proposed techniques reduce the amount of computations performed by temporal and inter-view predictions significantly with very small PSNR loss and bit rate increase. We also propose a low energy adaptive H.264 MVC motion estimation hardware for implementing the temporal and inter-view predictions including the proposed computation reduction techniques. The proposed hardware is implemented in Verilog HDL and mapped to a Xilinx Virtex-6 FPGA. The FPGA implementation is capable of processing 30 × 8 = 240 frames per second (fps) of CIF (352 × 288) size eight view video sequence or 30 × 2 = 60 fps of VGA (640 × 480) size stereo (two views) video sequence. The proposed techniques reduce the energy consumption of this hardware significantly.     

基于帧内预测模式多划分的HEVC鲁棒视频水印算法

针对现有基于高效视频编码（HEVC）标准的水印算法鲁棒性不足的问题,提出一种基于帧内预测模式多划分的HEVC鲁棒视频水印算法。首先,针对嵌入水印后帧内误差传播的问题,对4×4亮度块进行可嵌区域的选择,并计算4×4亮度块的纹理方向;其次,将33种角度预测模式划分为四种模式集,依次记为：上水平、下水平、上垂直、下垂直;最后,将当前以及下一待嵌入水印的值与模式集建立映射关系,通过判断当前4×4块属于哪个模式集来进行水印的嵌入,并将33种角度模式截断为其中一种模式集。解码端通过纹理方向和预测模式集提取水印。实验结果表明,所提算法的平均峰值信噪比维持不变,且在重编码攻击下的误码率（BER）为14.1%。由此可知,该算法对视频质量影响很小,在鲁棒性上可以抵抗重编码的攻击。     

HEVC-based lossless intra coding for efficient still image compression

Latest advancements in capture and display technologies demand better compression techniques for the storage and transmission of still images and video. High efficiency video coding (HEVC) is the latest video compression standard developed by the joint collaborative team on video coding (JCTVC) with this objective. Although the main design goal of HEVC is the compression of high resolution video, its performance in still image compression is at par with state-of-the-art still image compression standards. This work explores the possibility of incorporating the efficient intra prediction techniques employed in HEVC into the compression of high resolution still images. In the lossless coding mode of HEVC, sample- based angular intra prediction (SAP) methods have shown better prediction accuracy compared to the conventional block-based prediction (BP). In this paper, we propose an improved sample-based angular intra prediction (ISAP), which enhances the accuracy of the highly crucial intra prediction within HEVC. The experimental results show that ISAP in lossless compression of still images outclasses archival tools, state-of-the-art image compression standards and other HEVC-based lossless image compression codecs.     

Implementation of a cost-shared transform architecture for multiple video codecs

The paper presents a cost-shared architecture to compute multiple integer discrete cosine transform (Int-DCT) of four video codecs—AVS, H.264/AVC, VC-1 and HEVC (under development). Based on the symmetric structure of the matrices and the similarity in matrix operation, we develop a generalized “decompose and share” algorithm to compute both 4 × 4 and 8 × 8 Int-DCT. The algorithm is later applied to the video codecs. The hardware share approach ensures maximum circuit reuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significantly. The design is implemented on FPGA and later synthesized in CMOS 0.18 μm technology.     

Digital video watermarking based on intra prediction modes for audio video coding standard

Digital video watermarking provides means for carrying information targeted for synchronization, error resilience or copyright protection. However, it is difficult to get a good trade-off between the embedding capacity, imperceptibility and efficiency. In this paper, a novel digital video watermarking algorithm based on intra prediction modes of AVS (audio video coding standard) is proposed. The algorithm hides one bit in each qualified intra 8 × 8 luma block by modifying intra 8 × 8 prediction modes based on the mapping rules between the modes and hidden bits. The specific positions of the host 8 × 8 blocks are determined by the features of every block and a position template indicated by the key. Watermark information can be retrieved by decoding the intra prediction modes from bitstream, requiring neither original media nor complete video decoding. Experimental results show that the proposed algorithm has little impact on video quality and video stream features. A comparatively high embedding rate is obtained with little impact on bit rate.     

Fast HEVC I-frame coding based on strength of dominant direction of CUs

High efficiency video coding (HEVC), the latest international video coding standard, greatly outperforms previous standards such as H.264/AVC in terms of coding bitrate and video quality. The coding efficiency improvement in HEVC is achieved by introducing several new techniques such as recursive quad-tree structure and increased number of intra prediction modes. However, computational load is also increased due to employing the new techniques. In this paper, we propose a solution for fast I-frame coding in HEVC standard using homogeneity of Coding Units (CUs). The proposed solution consists of two stages. In the first stage, we evaluate CU homogeneity by computing a parameter named dominant direction strength and predict CU size by this means. In the second stage, we select 11 modes out of 35 for the specified CU size based on dominant direction of the CU. Experimental results indicate that the proposed method achieves on average 45.8 % reduction on coding time, with very similar coding efficiency as the HEVC reference software. Moreover, we designed tree-stage pipelined architecture for our method which can operate at 235 MHz maximum clock rate which means it can be used for real-time coding of all intra configuration of HEVC videos up to level 6.2.     

A novel architecture design for VLSI implementation of integer DCT in HEVC standard

This paper presents novel hardware of a unified architecture to compute the 4?×?4, 8?×?8, 16?×?16 and 32?×?32 efficient two dimensional (2-D) integer DCT using one block 1-D DCT for the HEVC standard with less complexity and material design. As HEVC large transforms suffer from the huge number of computations especially multiplications, this paper presents a proposition of a modified algorithm reducing the computational complexity. The goal is to ensure the maximum circuit reuse during the computation while keeping the same quality of encoded videos. The hardware architecture is described in VHDL language and synthesized on Altera FPGA. The hardware architecture throughput reaches a processing rate up to 52 million of pixels per second at 90 MHz frequency clock. An IP core is presented using the embedded video system on a programmable chip (SoPC) for implementation and validation of the proposed design. Finally, the proposed architecture has significant advantages in terms of hardware cost and improved performance compared to related work existing in the literature. This architecture can be used in ultra-high definition real-time TV coding (UHD) applications.

     

基于菱形编码的视频信息隐藏算法

针对基于视频帧内预测模式调制的信息隐藏算法嵌入容量较小、比特率上升较明显等问题,提出一种基于菱形编码的帧内视频信息隐藏算法。该算法基于高效视频编码（HEVC）,将相邻两个4×4块预测模式组成模式对,采用改进的菱形编码算法指导模式调制和信息嵌入过程;并采取二次编码方式在保留原始平台最优编码划分下进行第二次隐秘信息嵌入编码,在保证嵌入量的同时抑制帧内失真漂移。实验结果表明：所提算法峰值信噪比（PSNR）值下降在0.03dB以内,码率增长低于0.53%,嵌入量有大幅提升,并能很好地保证视频主客观质量。     

基于梯度的H.265/HEVC帧内预测硬件加速算法研究

HEVC即H.265,是目前最新的视频编码标准。相比于前一代视频编码标准,H.265/HEVC虽然能够明显改善视频压缩效率,但是却带来了更高的计算复杂度,尤其是在帧内预测过程中。为了解决这个问题,提出一种基于梯度的帧内预测硬件加速算法来跳过一些帧内预测模式和划分深度的预测过程,从而达到减少计算的目的。利用图像梯度信息来粗略估计编码单元的纹理方向和纹理复杂度,其中纹理方向用来估计编码单元的最优帧内预测方向,纹理复杂度用来判断是否跳过当前划分深度的预测编码过程。实验表明,相比于H.265/HEVC测试模型HM16.18,本文提出的算法能够减少6059%的编码时间,仅造成0.38 dB的BD PSNR减少和8.52%的BD-Rate增加。     

Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction

A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 219 MHz for Xilinx Virtex 6 and is capable to process real time 110 1080p frames per second or 24 4K frames per second.     

A multiplierless pruned DCT-like transformation for image and video compression that requires ten additions only

A multiplierless pruned approximate eight-point discrete cosine transform (DCT) requiring only ten additions is introduced. The proposed algorithm was assessed in image and video compression, showing competitive performance with state-of-the-art methods. Digital synthesis in 45 nm CMOS technology up to place-and-route level indicates clock speed of 288 MHz at a 1.1 V supply. The \(8\times 8\) block rate is 36 MHz. The DCT approximation was embedded into HEVC reference software; resulting video frames, at up to 327 Hz for 8-bit RGB HEVC, presented negligible image degradation.     

Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder

This paper presents the architecture of the high-throughput compensator and the interpolator used in the motion estimation of the H.265/HEVC encoder. The architecture can process 8×8 blocks in each clock cycle. The design allows the random order of checked coding blocks and motion vectors. This feature makes the architecture suitable for different search algorithms. The interpolator embeds 64 multiplierless reconfigurable filter cores to support computations for different fractional-pel positions. Synthesis results show that the design can operate at 200 and 400 MHz when implemented in FPGA Arria II and TSMC 90 nm, respectively. The computational scalability enables the proposed architecture to trade the throughput for the compression efficiency. If 2160p@30fps video is encoded, the design clocked at 400 MHz can check about 100 motion vectors for 8×8 blocks.     

自适应阈值的宏块MAD快速帧内算法

最新的视频压缩标准H.264/AVC具有极高的压缩率,但其算法极其复杂,编码时间较长,无法达到实时应用的要求。针对其帧内预测算法的特点,提出了一种基于MAD的自适应阈值快速帧内预测算法。算法充分利用宏块的MAD（平均绝对误差,Mean Absolute Differences）信息及时空相关性,在进行帧内预测之前先对宏块预判,同时采用自适应阈值的方法在帧内4×4（I4）和帧内16×16（I16）预测模式之间快速进行选择;然后针对I4预测,采用阈值法在9种预测模式间快速选择,从而减少了算法的复杂度,提高了压缩速度。实验结果表明,所提的算法在码率只有少许增加的情况下,编码时间平均减少61.3%,PSNR值基本不变。     

HEVC optimization based on human perception for real-time environments

High-Efficiency Video Coding (HEVC) is the new emerging video coding standard of the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG). The HEVC standard provides a significant improvement in compression efficiency in comparison with existing standards such as H264/AVC by means of greater complexity. In this paper we will examine several HEVC optimizations based on image analysis to reduce its huge CPU, resource and memory expensive encoding process. The proposed algorithms optimize the HEVC quad-tree partitioning procedure, intra/inter prediction and mode decision by means of H264-based methods and spatial and temporal homogeneity analysis which is directly applied to the original video. The validation process of these approaches was conducted by taking into account the human visual system (HVS). The adopted solution makes it possible to perform HEVC real time encoding for HD sequences on a low cost processor with negligible quality loss. Moreover, the frames pre-processing leverages the logic units and embedded hardware available on an Intel GPU, so the execution time of these stages are negligible for the encoding processor.

     

基于纹理特征的H.264帧内预测快速算法

H.264/AVC是最新的视频压缩编码标准,在帧内预测过程中,采用了率失真优化技术（RDO）进行预测模式的选择,使编码性能得到显著提高,但同时编码复杂度和计算量也明显增加。研究了现有的典型快速帧内预测算法,并提出一种融合宏块平坦性特征和4×4块纹理特征的快速帧内预测算法。算法通过判断宏块的平坦性提前选定块大小,根据4×4块内部纹理特征,确定预测模式集,降低算法复杂度。实验结果表明,较之JM95,在峰值信噪比(PSNR)基本不变,输出码率略有升高的情况下,本文算法对一个宏块的RDO计算次数平均降低了71.3%。     

利用时空相关性的HEVC帧内编码块快速划分

目的 为了提升高效视频编码（HEVC）的编码效率,使之满足高分辨率、高帧率视频实时编码传输的需求。由分析可知帧内编码单元（CU）的划分对HEVC的编码效率有决定性的影响,通过提高HEVC的CU划分效率,可以大大提升HEVC编码的实时性。方法 通过对视频数据分析发现,视频数据具有较强的时间、空间相关性,帧内CU的划分结果也同样具有较强的时间和空间相关性,可以利用前一帧以及当前帧CU的划分结果进行预判以提升帧内CU划分的效率。据此,本文给出一种帧内CU快速划分算法,先根据视频相邻帧数据的时间相关性和帧内数据空间相关性初步确定当前编码块的编码树单元（CTU）形状,再利用前一帧同位CTU平均深度、当前帧已编码CTU深度以及对应的率失真代价值决定当前编码块CTU的最终形状。算法每间隔指定帧数设置一刷新帧,该帧采用HM16.7模型标准CU划分以避免快速CU划分算法带来的误差累积影响。结果 利用本文算法对不同分辨率、不同帧率的视频进行测试,与HEVC的参考模型HM16.7相比,本文算法在视频编码质量基本不变,视频码率稍有增加的情况下平均可以节省约40%的编码时间,且高分辨率高帧率的视频码率增加幅度普遍小于低分辨率低帧率的视频码率。结论 本文算法在HEVC的框架内,利用视频数据的时间和空间相关性,通过优化帧内CU划分方法,对提升HEVC编码,特别是提高高分辨率高帧率视频HEVC编码的实时性具有重要作用。     

Fast intra prediction algorithm based on texture analysis for 3D-HEVC encoders

The advances in display technologies and the growing popularity of 3D video systems have attracted more consumers for 3D viewing experiences, and, consequently, the demand for storage and transmission of 3D video content is increasing. To cope with this demand, a 3D video extension of high-efficiency video coding (HEVC) standard is being developed and near the final standardization stage. The upcoming 3D-HEVC standard is expected to provide higher encoding efficiency than its predecessors, supporting multiple views with high resolution, at a cost of considerable increase in computational complexity, which can be an obstacle to its use in real-time applications. This article proposes a novel complexity reduction algorithm developed to optimize the 3D-HEVC intra mode decision targeting real-time video processing for consumer devices with limited computational power, such as 3D camcorders and smartphones equipped with multiple cameras and depth acquisition capabilities. The proposed algorithm analyzes the texture frames and depth maps to estimate the orientation of edges present in the prediction unit data, speeding up the intra prediction process and reducing the 3D-HEVC encoding processing time. Experimental results demonstrate that the proposed algorithm can save 26 % in computational complexity on average with negligible loss of encoding efficiency. This solution contributes to make more feasible the compression of 3D videos targeting real-time applications in power-constrained devices.     

ZLBM: zero level binary mapping technique for video security

In recent days, providing security to data is a crucial and critical task in many image processing applications. Specifically, video security is an important and demanding concept. For this purpose, some of the embedding, encoding and decoding techniques are mentioned in existing works, but it has some drawbacks such as increased time complexity, computational complexity and memory consumption. Moreover, it does not provide high security during video transmission. To overcome all these issues, a new technique, namely, Zero Level Binary Mapping (ZLBM) is proposed in this paper for video embedding scheme. The motivation of this paper is to provide high security during video transformation by using the video steganography technique. At first, the cover and stego videos are given as the inputs and it will be converted into the video frames for further processing. Here, the Fuzzy Adaptive Median Filtering (FAMF) technique is employed to remove the impulse noise in the video frames. Then, the pixels in the filtered frames are grouped by using the block wise pixel grouping technique. After that, the frames are embedded with the help of ZLBM technique and encoded based on the patch wise code formation technique. On the receiver side, the inverse ZLBM and block wise pixel regrouping techniques are applied to get the original cover and stego videos. The novel concept of this paper is the use of ZLBM and patch wise code formation techniques for video embedding and compression. The main advantages of the proposed system are high security, good quality and reduced complexity. The experimental results evaluate the performance of the proposed video embedding technique in terms of Peak Signal-to-Noise Ratio (PSNR), Mean Squared Error (MSE), Compression Ratio (CR), Bits Per Pixel (BPP) and Signal-to-Noise Ratio (SNR).     

面向CPU-GPU平台的HEVC编码器优化

针对CPU-GPU平台提供了一种能显著降低高效视频编码(high efficiency video coding,简称HEVC)复杂度的优化方案.根据编码器的复杂度分布及不同模块的特点,针对帧内预测、帧间预测以及环路滤波分别进行了优化.在帧内预测中,基于相邻编码单元(coding unit,简称CU)之间的相关性,提出了一种CU的深度决策方法以及一种减少率失真优化(RDO)的模式数量的方法,降低了帧内编码的复杂度.在帧间预测中,提出将耗时最大的运动估计模块完善在图形处理单元(GPU)上,通过中央处理单元(CPU)和GPU的流水线工作获得了明显的加速,并基于预测残差的能量提出了一种编码单元提前终止划分的方法,有效降低了帧间编码复杂度.在环路滤波中,提出了一种GPU端的自适应样本点补偿(sample adaptive offset,简称SAO)参数决策方法及去块滤波方法,有效分担了CPU端的复杂度.上述优化实现在HM16.2上,实验结果表明,提出的优化方案可以获得高达68%的编码复杂度节省,而平均性能损失仅为0.5%.     

基于Logistic和Arnold变换的HEVC选择性加密方案

为了有效地保护视频信息，根据H.265/高效视频编码（HEVC）的特点，提出一种变换系数置乱和语法元素加密相结合的方案。针对变换单元（TU），利用Arnold变换对4×4大小的TU进行置乱，同时设计了一种移位加密器，根据TU的直流电（DC）系数近似分布规律对加密器进行初始化，并用Arnold变换生成加密映射对8×8、16×16、32×32大小TU的DC系数进行移位加密。针对熵编码过程中部分采用旁路编码的语法元素，利用Logistic混沌序列进行加密。加密后的视频峰值信噪比（PSNR）和结构相似性（SSIM）分别平均下降了26.1 dB和0.51，压缩率仅降低了1.126%，也仅带来0.170%的编码时间增长。实验结果表明，在保证较好的加密效果、对比特率影响较小的前提下，所提方案具有较小的额外编码开销，适用于实时视频应用。