FPGA-based architecture for real time segmentation and denoising of HD video

The identification of moving objects is a basic step in computer vision. The identification begins with the segmentation and is followed by a denoising phase. This paper proposes the FPGA hardware implementation of segmentation and denoising unit. The segmentation is conducted using the Gaussian mixture model (GMM), a probabilistic method for the segmentation of the background. The denoising is conducted implementing the morphological operators of erosion, dilation, opening and closing. The proposed circuit is optimized to perform real time processing of HD video sequences (1,920 × 1,080 @ 20 fps) when implemented on FPGA devices. The circuit uses an optimized fixed width representation of the data and implements high performance arithmetic circuits. The circuit is implemented on Xilinx and Altera FPGA. Implemented on xc5vlx50 Virtex5 FPGA, it can process 24 fps of an HD video using 1,179 Slice LUTs and 291 Slice Registers; the dynamic power dissipation is 0.46 mW/MHz. Implemented on EP2S15F484C3 StratixII, it provides a maximum working frequency of 44.03 MHz employing 5038 Logic Elements and 7,957 flip flop with a dynamic power dissipation of 4.03 mW/MHz.     

A parallel architecture for performing mail sorting in real time

This paper describes a special-purpose embedded multiprocessor architecture developed for performing real-time multi-line optical character recognition (MLOCR). MLOCR is a computationally intensive real-time application involving pattern recognition, character image extraction, gray-scale thresholding, rotation and scaling of individual characters, and character identification. The computational complexity of the MLOCR application dictated the development of custom hardware in a parallel processing environment in order to meet the real-time system requirements. The overall system organization is described, along with the functional partitioning of algorithms onto processors, development of specific custom hardware to implement the algorithms in real time, interprocess communications, and system control.     

Robust segmentation and analysis of DNA microarray spots using an adaptative split and merge algorithm

Microarray images push to their limits classical analysis methods, since gene spots are often poorly contrasted, ill defined and of irregular shapes. These characteristics hinder a robust quantification of corresponding values for red and green intensities as well as their R/G ratio. New approaches are thus needed to ensure accurate data extraction from these images. Herein we present an automatic non-supervised algorithm for a fast and accurate spot data extraction from DNA microarrays. The method is based on a split and merge algorithm, relying on a Delaunay triangulation process, allowing an incremental partition of the image into homogeneous polygons. Geometric properties of triangles as well as homogeneity criteria are defined according to the specificities of microarray image signals. The method is first assessed on simulated data, and then compared with GenePix and Jaguar Softwares. Results in segmentation and quantification are superior to those obtained from a number of standard techniques for spot extraction.     

The parallel odd-even merge algorithm

This paper briefly describes the implementation of the odd-even merge algorithm on a parallel MIMD computer and discusses its computational complexity.     

A parallel sort merge join algorithm for managing data skew

A parallel sort-merge-join algorithm which uses a divide-and-conquer approach to address the data skew problem is proposed. The proposed algorithm adds an extra, low-cost scheduling phase to the usual sort, transfer, and join phases. During the scheduling phase, a parallelizable optimization algorithm, using the output of the sort phase, attempts to balance the load across the multiple processors in the subsequent join phase. The algorithm naturally identifies the largest skew elements, and assigns each of them to an optimal number of processors. Assuming a Zipf-like distribution of data skew, the algorithm is demonstrated to achieve very good load balancing for the join phase, and is shown to be very robust relative, among other things, to the degree of data skew and the total number of processors     

Model-based segmentation and tracking of head-and-shoulder video objects for real time multimedia services

A statistical model-based video segmentation algorithm is presented for head-and-shoulder type video. This algorithm uses domain knowledge by abstracting the head-and-shoulder object with a blob-based statistical region model and a shape model. The object segmentation problem is then converted into a model detection and tracking problem. At the system level, a hierarchical structure is designed and spatial and temporal filters are used to improve segmentation quality. This algorithm runs in real time over a QCIF size video, and segments it into background, head and shoulder three video objects on average Pentium PC platforms. Due to its real time feature, this algorithm is appropriate for real time multimedia services such as videophone and web chat. Simulation results are offered to compare MPEG-4 performance with H.263 on segmented video objects with respects to compression efficiency, bit rate adaptation and functionality.     

A parallel algorithm for stochastic image segmentation

A parallel algorithm for syntactic image segmentation is introduced. Stochastic tree grammar is used as a context-generating model. It is shown that when this context-generating process is in the equilibrium state, a matched filter can be designed and applied in parallel to the image. This process can be used for image segmentation in a syntactic pattern recognition system to enhance the performance of the succeeding recognition process.     

A parallel architecture for discrete relaxation algorithm

Discrete relaxation techniques have proven useful in solving a wide range of problems in digital signal and digital image processing, artificial intelligence, operations research, and machine vision. Much work has been devoted to finding efficient hardware architectures. This paper shows that a conventional hardware design for a Discrete Relaxation Algorithm (DRA) suffers from O(n2m3) time complexity and O(n2m2) space complexity. By reformulating DRA into a parallel computational tree and using a multiple tree-root pipelining scheme, time complexity is reduced to O(nm), while the space complexity is reduced by a factor of 2. For certain relaxation processing, the space complexity can even be decreased to O(nm). Furthermore, a technique for dynamic configuring an architectural wavefront is used which leads to an O(n) time highly concurrent DRA3 architecture.     

基于FPGA的KLT特征点多层次归并排序

KLT算法已在多个领域得到成功的应用,其中特征点的排序是用来选择好的特征点跟踪的关键。针对传统排序算法计算耗时、实时性差的缺点,提出一种可并行的多层次归并排序算法并在FPGA中实现了其并行计算,同时分析了其周期精确的计算时间。结果表明该归并排序算法可以[O(N)]的时间复杂度完成特征点的排序,能够满足高清分辨率的图像/视频数据中KLT特征点排序的实时性要求。     

Image seaming for segmentation on parallel architecture

Some basic problems encountered when assembling the results of image analysis on architectures with coarse parallelism are discussed. The emphasis is on strategies that minimize the distortion in the final result caused by processing image tiles independently. Methods are presented that can be used to reduce the disparity between the results of processing each title independently and processing each as part of a whole image. A seaming algorithm has been constructed to seam the tiles with the results of region segmentation using the gray-level mean difference or maximum-minimum criteria. Experimental results, obtained on a Sequent machine and a Sun 3/160 workstation, are given to illustrate the performance of the algorithm     

基于分水岭和区域合并的图像分割算法*

提出一种应用分水岭与区域合并相结合的图像分割算法.本方法首先利用数学形态学分水岭算法对图像进行分割,然后对分割后的图像进行相似区域合并,以减少分水岭方法产生的过分割现象,从而得到较好的分割效果.     

The parallel neighbour sort and 2-way merge algorithm

This paper briefly describes the implementation of the neighbour sort and 2-way merge algorithms on a parallel MIMD computer and analyses their computational complexity.     

REAKT: A real time architecture for knowledge based systems

Expert systems have now reached maturity and an ever growing number of applications make use of this technology. Nevertheless, specific requirements of real time applications have significantly slowed down the use of these techniques in this area: this is first due to incompatibilities between time and memory requirements of AI algorithms and real time specificities, but also to a lack of adaptation to the growing complexity of these systems.In this paper a real time architecture for Knowledge Based Systems: REAKT (Real Time Knowledge Tool) which aims at combining the expressiveness and power of Knowledge Based Systems with the efficiency and predictability of real time systems is presented.     

融合聚类和分级区域合并的彩色图像分割方法

提出了一种融合聚类的分级区域合并彩色图像分割方法。为平滑图像且保持良好边缘,首先用均值偏移算法进行滤波,在此基础上运用改进的k均值聚类方法在颜色空间对图像进行聚类,形成图像的初始分割区域。融合颜色、空间和邻域信息度量区域的距离,对初始分割区域进行分级合并,直至满足停止区域合并的准则。利用形态学腐蚀与膨胀算法对区域边缘进行平滑。仿真结果表明,算法的分割结果符合人类主观视觉感知,具有良好的一致性。     

全互联视频会议实时数据传输路由算法设计*

针对NAT环境下参与用户网络类型、网络状况往往不一致的情况,提出一种动态节点转发的实时多媒体数据传输技术。采用数据发送节点基于最优节点路由算法将数据发送给多媒体系统中的某些节点,然后由这些节点及下一批被选中接收的节点将数据经过多次转发,发送给系统中的其他节点,最终实现系统中各节点多媒体数据全互联。     

河道监控视频的运动对象分割算法

针对内河航道监控视频的特点,提出一种基于背景差法的对象分割算法。首先在HSI颜色空间里利用像素的色调和亮度对其进行归类;然后利用基于块处理的方法确定背景像素,并在背景缓慢变化和急速变化时,采用定时和实时的背景重构方法进行背景更新;最后利用背景差提取运动对象。     

MPEG-4实时视频传输的拥塞控制算法的改进

提高视频图像的传输质量是网络拥塞控制方面的重要研究课题,在阐述了码率控制技术和实时视频传输的构架后,分析了基于丢包率和双丢包率阈值门限的拥塞控制机制以及VM8码率控制算法,指出了VM8码率控制算法的不足,所在并进行了相应的改进.根据当前丢包率,对未来的发送速率的变化做出预测,从而动态地决定缓冲区目标水位参数,使得改进后的算法对发送速率具有一定的预测性.实验证明,改进后的算法有效地提高了编码后的图像质量.     

划时区分段的动态时间规整算法

轨迹聚类是城市交通数据挖掘的重点之一,交通轨迹聚类算法是按照一定的相似度指标将轨迹划分成若干个类簇。在复杂的路网环境下,针对目前如DTW、SDTW等相似度计算方法准确性不高的问题进行了研究,提出了一种划时区分段的动态时间规整算法（SDTW+）进行相似度计算。该算法充分考虑了轨迹形状因素,能有效提高准确性。实验部分利用不同相似度算法,并结合层次聚类算法对实际车辆轨迹进行聚类,最终以平均轮廓系数和聚类成功率为评价指标,判断不同相似度算法的聚类效果。试验结果表明,采用所提算法相对于采用DTW、SDTW的平均轮廓系数分别提高33.86%,12.94%,同时聚类成功率也得到一定提高。