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1.
Chevalier J. de Nanclas M. Filion L. Benny O. Rondonneau M. Bois G. El Mostapha Aboulhamid 《Design & Test of Computers, IEEE》2006,23(2):148-158
This article presents a design environment that provides an interface for user-written SystemC modules that model application software to make calls to a real-time operating system (RTOS) kernel and cosimulate with user-written SystemC hardware modules. The environment also facilitates successive refinement through three abstraction layers for hardware-software codesign suitable for embedded-system design. 相似文献
2.
We describe a SystemC library for specifying, modeling, and simulating hardware pipelines. The library includes a set of overloaded operators defining a pipeline expression language that allows the user to quickly specify the architecture of the pipeline. The pipeline expression is used to derive the connectivity of the SystemC modules that define the stages of the pipeline and to automatically insert latches and control modules between the stages to handle the proper routing of transactions through pipeline. Using the SystemC simulator the pipeline can then be simulated and evaluated. The pipeline expression language sits on top of SystemC, exposes all of the features of C++ and SystemC enabling the user to specify, evaluate, and analyze pipeline architectures. 相似文献
3.
近来用SystemC进行嵌入式软件建模研究非常活跃,目前尚不能用SystemC直接模拟嵌入式软件中常见的抢占式进程调度的行为。本文在详细的分析了SystemC模拟内核的基础上,提出将进程划分为一个一个不可分割的原子进程单元(APUs),作为进程调度的最小单位,并构造出一个RTOS抽象层实现任务抢占、实时调度、中断处理等功能,用以实现抢占式进程调度行为的建模和验证。实例表明,采用文中提出的方法,设计者在系统抽象层就可以进行多任务系统的动态调度如中断、抢占的模拟和验证,有效地提高了设计能力。 相似文献
4.
系统级建模是大规模集成电路设计的一个重要阶段,它实现了设计从文本规范向功能实现的过渡,传统方法中一直使用硬件描述语言(HDL)来完成系统级建模,其弊端在于建模的效率低不适应如今SoC设计的要求。SystemC作为一种基于C 语言的新型硬件设计语言较已有的HDL语言在系统级建模、软硬件协调设计方面更具优势,因此也更适用于SoC的设计建模,该文介绍了SystemC的最新版本SystemC2.0的使用特点以及如何利用其进行SoC顶层设计的方法,并通过对一个短消息平台的建模实例说明如何具体使用SystemC2.0,通过与传统方法的比较可以得出结论,SystemC可以迅速有效地实现SoC系统级的建模。 相似文献
5.
Peters D.K. Parnas D.L. 《IEEE transactions on pattern analysis and machine intelligence》2002,28(2):146-158
Before designing safety- or mission-critical real-time systems, a specification of the required behavior of the system should be produced and reviewed by domain experts. After the system has been implemented, it should be thoroughly tested to ensure that it behaves correctly. This is best done using a monitor, a system that observes the behavior of a target system and reports if that behavior is consistent with the requirements. Such a monitor can be used both as an oracle during testing and as a supervisor during operation. Monitors should be based on the documented requirements of the system. If the target system is required to monitor or control real-valued quantities, then the requirements, which are expressed in terms of the monitored and controlled quantities, will allow a range of behaviors to account for errors and imprecision in observation and control of these quantities. Even if the controlled variables are discrete valued, the requirements must specify the timing tolerance. Because of the limitations of the devices used by the monitor to observe the environmental quantities, there is unavoidable potential for false reports, both negative and positive, This paper discusses design of monitors for real-time systems, and examines the conditions under which a monitor will produce false reports. We describe the conclusions that can be drawn when using a monitor to observe system behavior 相似文献
6.
使用SystemC进行基于事务的验证 总被引:2,自引:0,他引:2
分析了使用SystemC的基于事务的验证方法。它应用于一个具体项目的开发,并与传统的验证方法作了对比,证明它在验证效率和验证环境设计效率上均有明显优势。 相似文献
7.
Transaction-Level Models (TLM) are used for the early validation of embedded software. A TL model is a virtual prototype of
the hardware part of a System-on-a-Chip (SoC). When using SystemC for transaction level modeling, the main parallel entities
of the hardware platform (processors, DMAs, bus arbiters, etc.) are modeled by asynchronous processes, which are scheduled
at simulation time. The specification of this scheduling mechanism is non-deterministic; the set of all possible schedulings
of the parallel activities represents the physical parallelism faithfully. Moreover TL models may contain loose timing annotations
(intervals for instance), and the set of all possible values of time in these intervals is also meant to represent the hardware
behaviors faithfully.
However, any simulation engine is built on a deterministic scheduler, and at runtime will use specific values in the time
intervals. This means that only a very small subset of all the possible schedulings and timings are exhibited during simulation.
Some bugs may be missed if they are due to some behaviors of the hardware that are represented by other schedulings or timings. 相似文献
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使用SystemC设计UART IP核 总被引:1,自引:0,他引:1
IP核技术是系统芯片SOC设计中的一个重要部分,如何实现和利用IP核减小SOC设计的复杂度成为目前微电子设计中的热点。将UART通信技术核心功能设计成紧凑的IP核,易于应用在各种嵌入式环境。本文说明了如何使用SystemC语言工具设计该IP核。 相似文献
10.
采用SystemC2.0,结合AMBA片上总线,探讨了在事务级的建模方法,并结合JPEG2000中的无损小波提升算法给出建模实例。介绍TsystemC2.O通过指令集模拟器建立事务级处理器模型的一般方法和步骤。 相似文献
11.
In this paper, we first introduce a profile-driven online page migration scheme and investigate its impact on the performance of multithreaded applications. We use centralized lightweight, inexpensive plug-in hardware monitors to profile the memory access behavior of an application, and then migrate pages to memory local to the most frequently accessing processor. We also investigate the use of several other potential sources of data gathered from hardware monitors and compare their effectiveness to using data from centralized hardware monitors. In particular, we investigate the effectiveness of using cache miss profiles, Translation Lookaside Buffer (TLB) miss profiles and the content of the on-chip TLBs using the valid bit information. Moreover, we also introduce a modest hardware feature, called Address Translation Counters (ATC), and compare its effectiveness with other sources of hardware profiles. 相似文献
12.
提出一个基于SystemC的可配置嵌入式系统快速虚拟原型平台,它具有典型的片上系统结构,支持多层总线架构.作为SystemC事务处理级模型,该平台支持快速仿真和通信细化.将此平台应用于IEEE 802.11媒体访问控制器的设计,目前该系统正处于板级调试过程中. 相似文献
13.
A technique is presented for constructing an operating system as a hierarchical set of monitors. The hierarchy reflects and reinforces the system structure, and extends down to the system nucleus itself. The nucleus is in fact treated as a specialized monitor for handling the central processor. The technique has been used to write a small pilot system for a DEC PDP-15, and experience with the system is reported. The mutual exclusion problem for monitor procedures is discussed, and a viable solution suggested. 相似文献
14.
Real-time systems connected through packet networks belong to the family of networked control systems, and they can be easily destabilized by communication delay and packet losses, when they are not properly compensated. The largest part of the solutions available in the literature are mainly based on control and system theory where the parameters of the network are assumed to be given. This classical approach could be improved by designing at the same time the network, e.g., by introducing quality-of-service guarantees as currently done in teleconference applications. Such control/network co-design needs a simulation framework where both aspects are properly and jointly addressed. The paper addresses this topic starting from the discussion of its critical issues, and then proposing an accurate co-simulation tool based on SystemC and Matlab/Simulink. SystemC will be used for the network simulation and protocol design whereas Matlab/Simulink for plant modeling and control design. 相似文献
15.
人们提出了软件硬件协同设计的设计方法,以克服传统的将软件和硬件分开的设计方法对于SOC的设计存在的缺陷。SyStenlC是顺应这种发展趋势而产生的系统级描述语言。它是一种通过类对象扩展和基于C/C 的建模平台,支持系统级软硬件协同设计、仿真、验证、软硬件协同设计的系统级描述语言。本文介绍了系统级描述语言SySternC在集成电路设计中的应用,讨论了基于SyStemC的集成电路设计的设计流程、设计优势及其发展趋势。 相似文献
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17.
石柯 《小型微型计算机系统》2003,24(4):763-765
本文提出了一种基于SystemC的嵌入式系统设计方法,SystemC是OSCI(Open SystemC Initiative)组织制定和维护的一种开放源代码的C++建模平台,提供支持硬件建模和仿真的C++类库及相应的仿真内核,SystemC消除了一直存在于系统级设计和硬件设计之间的语言隔阂,支持在整个嵌入式系统设计流程内使用C++来统一描述硬件和软件,基于C++的系统功能定义能够方便有效地映为硬件实现部分和软件实现部分,该方法同传统的设计方法相比更加灵活和有效。 相似文献
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Systems simulated by using the SystemC language are usually parallel and, therefore, may contain synchronization errors. Data races make up one widespread type of synchronization errors. In this paper, an approach to data race error detection in SystemC programs based on the analysis of the static source code is proposed. Algorithms for analyzing SystemC programs without quantitative time are developed. These algorithms allow one to detect all the data races existing in the program. The efficiency of the approach is proved by the experimental results obtained from using the developed tool meant for error detection for a set of test programs. 相似文献
20.
P. D. Terry 《Software》1986,16(5):457-472
The concept of the monitor as a device for handling the problems of mutual exclusion and synchronization in a set of concurrent processes is now well understood. In addition to being of considerable theoretical interest, the monitor concept has been found suitable for the design of several practical operating systems. This paper discusses an implementation of monitors using a kernel written in Modula-2. 相似文献