共查询到18条相似文献,搜索用时 125 毫秒
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运算放大器不同剂量率的辐射损伤效应 总被引:2,自引:1,他引:1
对几种不同类型(TTL,CMOS,JFETBi,MOSBi)的典型星用运算放大器在不同剂量率(100,10,1及0.01rad(Si)/s)辐照下的响应规律及随时间变化的退火特性进行了研究.结果显示不同类型运放电路的辐照响应有明显差异:双极运放电路辐照剂量率越小,其损伤越大;CMOS运放电路对不同剂量率的响应并非线性关系,但不同剂量率辐照损伤的差异,可以通过与低剂量率相同时间的室温退火得到消除,本质上仍然是与时间相关的效应;JFET输入运放不仅有低剂量率辐照损伤增强效应存在,且辐照后还有明显的“后损伤”现象;PMOS输入运放的结果则表明,各辐照剂量率间的损伤无明显区 相似文献
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对几种不同类型(TTL,CMOS,JFET-Bi,MOS-Bi)的典型星用运算放大器在不同剂量率(100,10,1及0.01rad(Si)/s)辐照下的响应规律及随时间变化的退火特性进行了研究.结果显示不同类型运放电路的辐照响应有明显差异:双极运放电路辐照剂量率越小,其损伤越大;CMOS运放电路对不同剂量率的响应并非线性关系,但不同剂量率辐照损伤的差异,可以通过与低剂量率相同时间的室温退火得到消除,本质上仍然是与时间相关的效应;JFET输入运放不仅有低剂量率辐照损伤增强效应存在,且辐照后还有明显的"后损伤"现象;PMOS输入运放的结果则表明,各辐照剂量率间的损伤无明显区别. 相似文献
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针对具有低压触发特性的静电放电(electrostatic discharge,ESD)保护电路易闩锁的不足,本文结合CSMC0.6μm CMOS工艺,设计了一种可应用于ESD保护电路中的独立双阱隔离布局方案,这种方案不仅可以有效的阻断形成闩锁的CMOS器件固有纵向PNP与横向NPN晶体管的耦合,且兼容原有工艺而不增加版图面积。将此布局方案与常规保护环结构同时应用于笔者研制的具有低压快速触发特性双通路ESD保护电路中,通过流片及测试对比表明,该布局方案在不影响保护电路特性的同时,较常规保护环结构更为有效的克服了保护电路的闩锁效应,从而进一步提升了该保护电路的鲁棒性指标。本文的布局方案为次亚微米MOS ESD保护电路版图设计提供了一种新的参考依据。 相似文献
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本文简要描述了CMOS集成电路的闭锁机理,提出了消除CMOS集成电路闭锁的n~-/n~+外延加双保护环结构;把这种结构用于CC4066电路,在5.6×10~8Gy/s的γ瞬时剂量率下进行辐照实验,电路均不发生闭锁。最后得出,外延加双保护环结构,对中小规模电路而言,是一种消除CMOS电路闭锁的有效方法。 相似文献
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Two CMOS differential amplifiers, one that is intended for applications in which the input common-mode range is relatively limited, the complementary self-biased differential amplifier (CSDA), and one that is intended for applications in which the input common-mode range is bounded only by the supply voltages, the very-wide-common-mode-range differential amplifier (VCDA), are discussed. Both differ from conventional CMOS differential amplifiers in having fully complementary configurations and in being self-biased through negative feedback. The amplifiers have been applied as precision high-speed comparators in commercial VLSI CMOS integrated circuits 相似文献
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《IEEE transactions on circuits and systems. I, Regular papers》2008,55(7):1781-1793
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Liu Mengxin Han Zhengsheng Bi Jinshun Fan Xuemei Liu Gang Du Huan 《半导体学报》2009,30(1):104004-1-014004-7
Thin gate oxide radio frequency (RF) PDSOI nMOSFETs that are suitable for integration with 0.1 μm SO1 CMOS technology are fabricated, and the total ionizing dose radiation responses of the nMOSFETs having four different device structures are characterized and compared for an equivalent gamma dose up to 1 Mrad (Si), using the front and back gate threshold voltages, off-state leakage, transconductance and output characteristics to assess direct current (DC) performance. Moreover, the frequency response of these devices under total ionizing dose radiation is presented, such as small-signal current gain and maximum available/stable gain. The results indicate that all the RF PDSOI nMOSFETs show significant degradation in both DC and RF characteristics after radiation, in particular to the float body nMOS. By comparison with the gate backside body contact (GBBC) structure and the body tied to source (BTS) contact structure, the low barrier body contact (LBBC) structure is more effective and excellent in the hardness of total ionizing dose radiation although there are some sacrifices in drive current, switching speed and high frequency response. 相似文献
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Yo-Chuol Ho Ki-Hong Kim Floyd B.A. Wann C. Yuan Taur Lagnado I. O K.K. 《Solid-State Circuits, IEEE Journal of》1998,33(12):2066-2073
Four- and 13-GHz tuned amplifiers have been implemented in a partially scaled 0.1-1 μm CMOS technology on bulk, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS) substrates. The 4-GHz bulk, SOI, and SOS amplifiers exhibit forward gains of 14, 11, and 12.5 dB and Fmin's of 4.5 (bulk) and 3.5 db (SOS). The 13-GHz SOS and SOI amplifiers exhibit gains of 15 and 5.3 dB and Funn's of 4.9 and 7.8 dB. The 4-GHz bulk amplifier has the highest resonant frequency among reported bulk CMOS amplifiers, while the 13-GHz SOS and SOI amplifiers are the first in a CMOS technology to have tuned frequencies greater than 10 GHz. These and other measurement results suggest that it may be possible to implement 20-GHz tuned amplifiers in a fully scaled 0.1-1 μm CMOS process 相似文献
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分析了目前几种高性能连续时间CMOS电流比较器的优缺点,提出了一种新型CMOS电流比较器电路.它包含一组具有负反馈电阻的CMOS互补放大器、两组电阻负载放大器和两组CMOS反相器.由于CMOS互补放大器的负反馈电阻降低了它的输入、输出阻抗,从而使电压的变化幅度减小,所以该电流比较器具有较短的瞬态响应时间和较快的速度.电阻负载放大器的使用减小了电路的功耗.利用1.2μm CMOS工艺HSPICE模型参数对该电流比较器的性能进行了模拟,结果表明该电路的瞬态响应时间达到目前最快的CMOS电流比较器的水平,而功耗则低于这些比较器,具有最大的速度/功耗比.此外,该CMOS电流比较器结构简单,性能受工艺偏差的影响小,适合应用于高速/低功耗电流型集成电路中. 相似文献