Silicide pre-clean effects on NiPtSi thermal stability for 65 nm technologies and beyond

The effects of different surface preparations on NiPtSi thermal stability were studied. HF wet clean, argon sputter etch and remote plasma pre-clean were used as silicide pre-cleans prior to NiPt sputter deposition and subsequent silicidation on blanket and patterned Si wafers. NiPtSi was characterized using SIMS, ellipsometry, voltage contrast (ES25) testing and electrical performance measurements of 65 nm test structures. Results show that when an in situ remote plasma pre-clean is used in addition to a classical HF wet clean to remove native oxide from the Si substrate prior to NiPt deposition and silicidation, Rs uniformity and SRAM electrical performance as a function of thermal budget are significantly improved. Rs measurements of patterned wafers and SIMS analysis of blanket wafers strongly suggest that the absence of native oxide prior to NiPt deposition and the presence of fluorine at the NiPtSi/Si interface play a key role in improving NiPtSi thermal stability.     

硅外延工艺与基座的相关性研究

硅外延使用包封SiC的石墨基座,基座的尺寸及基座上承载槽的形貌和硅外延片的滑移位错直接相关。为使高温下Si片内产生的应力不超过滑移位错产生的临界应力,必须使Si片处于均匀的温区。实际使用表明,基座边缘热辐射及热量被气流带走使基座两个边缘温度急剧下降,必须对边缘温区进行补偿及装片时避开基座边缘一定距离;高温时Si片通过基座获得热量并发生形变,基座上承载槽的形貌设计必须兼顾厚度匀匀性及Si片高温时形变的方向。研究表明,金属沾污尤其是重金属催化作用及过腐蚀是影响基座寿命的关键因素。     

Large scale production of indium antimonide film for position sensors in automobile engines

We use low pressure MOVPE to grow indium antimonide films on groups of eight 3 inch GaAs wafers per run. The films are used for the production of magnetoresistive position sensors for the car industry. To meet the narrow specifications for automotive components, the standard deviation of the sheet resistivity, and the thickness of the films have been reduced below 1.5%. This uniformity is the result of an optimization process encompassing the determination of the best susceptor temperature and the optimum flow. The gas velocity was found to have a large impact on the uniformity of the layers. Rotation of the wafers and the use of an optimum gas velocity results in extremely uniform layers.     

Multi-wafer 3C-SiC thin films grown on Si(100) in a vertical HWLPCVD reactor

We report the latest results of the 3C-SiC layer growth on Si(100)substrates by employing a novel home-made horizontal hot wall low pressure chemical vapour deposition(HWLPCVD)system with a rotating susceptor that was designed to support up to three 50 mm-diameter wafers.3C-SiC film properties of the intrawafer and the wafer-to-wafer,including crystalline morphologies and electronics,are characterized systematically. Intra-wafer layer thickness and sheet resistance uniformity(σ/mean)of～3.40%and～5.37%have been achieved in the 3×50 mm configuration.Within a run,the deviations of wafer-to-wafer thickness and sheet resistance are less than 4%and 4.24%,respectively.     

Correlation analysis between pattern and non-pattern wafer for characterization of shallow trench isolation–chemical–mechanical polishing (STI–CMP) process

This study is about control of oxide removal amounts on the shallow trench isolation (STI) patterned wafers using removal rate and thickness of blanket (non-patterned) wafers. At first, the removal properties of plasma enhanced tetra-ethyl ortho-silicate (PETEOS) blanket wafers was investigated, and then it was compared with the removal properties and the planarization (step height) as a function of polishing time of the specific STI patterned wafers. We found that there is a relationship between the amount of oxide removal by blanket and patterned wafers. We analyzed this relationship, and the post-CMP thickness of patterned wafers could be controlled by removal rate and removal target thickness of blanket wafers. As the result of correlation analysis, we confirmed that there was the strong correlation between patterned and blanket wafers (correlation factor: 0.7109). So, we could confirm the repeatability as applying to STI CMP process from the linear formula obtained.     

Manufacturability issues related to transient thermal annealing oftitanium silicide films in a rapid thermal processor

Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSi_x films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSi_x films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses     

Hydrogen implanted silicon oxidation

The oxidation rate and the oxide thickness of the hydrogen ion implanted silicon wafers were examined. It was observed that the native oxide thickness is higher for the H⁺ implanted Si(100) compared to the Si(111). Also the native oxide thickness depended on the implanted hydrogen distribution. The thickness increased with the hydrogen con-centration. The oxide thickness after wet oxidization of the H⁺ implanted Si(111) was higher than that of the unimplanted wafers. The oxide thickness also depended on the resistivity of the H⁺ implanted Si wafers. The suggested explanation is that in high energy H⁺ implanted Si the oxidation rate is higher as a result of the higher diffusion and reaction kinetics. All these measurements were done with the assumption that the implanted and the unimplanted samples have the same indices of refraction for the oxide as well as for the substrate.     

Capless rapid thermal annealing of GaAs using a graphite susceptor

The results of experiments performed to evaluate the use of a commercially available rapid thermal annealer (RTA) with a graphite susceptor for capless rapid thermal annealing to activate implants in GaAs are reported. The interior of the susceptor was easily charged with As by annealing a sacrificial GaAs wafer. Wafers annealed face up in the charged susceptor showed no evidence of surface degradation (due to preferential loss of As) and no decrease in implant activation (peak doping) when compared to dielectric (SiO₂) capped anneals. Over 50 wafers have been annealed without recharging the susceptor. In addition, slip on 3-in wafers was almost completely eliminated due to the reduction of radial temperature gradients. It is concluded that capless RTA in a commercially available graphite susceptor appears to be a viable annealing technique for activating implants in GaAs and related III-V materials and is suitable for a production environment     

Heat flow modeling of chemical vapor deposition of tungsten for improved film thickness uniformity

The boundary element method is used to model the heat flow in a tungsten chemical vapor deposition (CVD W) reactor to determine the origin of the tungsten film thickness variation across a 125 mmp-type silicon wafer. The typical thickness nonuniformity is 7-10%. The model predicts temperature variations in the graphite susceptor which heats the wafers. The resulting temperature difference between the center and edge of a wafer can be up to 20 °C. Deposition rate experiments in a CVD W reactor confirm this. Experiments involving changes in the gas flow geometry have been conducted. It is concluded that the temperature gradient across the wafer, not the gas flow geometry, is the dominant factor controlling film thickness uniformity for this CVD W reactor.     

高温热氧化中SiO2层厚度的控制研究

本文介绍了Si热氧化的工艺过程和温度曲线,对热氧化生成的SiO2层厚度进行了理论计算和实际测定;并列出了７个ＳiO2样品的干,湿氧时间,理论计算值,实测值及产生的误差值,多数样件可控制在１５％左右（最优达７０％）;介绍了控制干,湿氧不相互干扰的管路系统,稳定水浴湿度９５℃的方法,分析了影响ＳiO2层厚度的石英管口径及氧气流量等因素。     

Spray coating of PMMA for pattern transfer via electron beam lithography on surfaces with high topography

Spray coating of polymethylmethacrylate (PMMA) as electron beam resist on non planar surfaces is presented as a reliable technique for deposition of uniform resist layers with adjustable thickness at wafer scale. In the experiments a commercial spray coating system with an ultrasonic spray nozzle was used. Parameters which influence the quality of the resist layer with respect to uniformity across a 4 in Si wafer, such as ultrasonic power and dispensed volume, were evaluated. The suitability of spray coated PMMA for the pattern transfer on surfaces with high topography was proven by PMMA spray coating of 8 μm deep trenches etched into Si wafers. The PMMA was then electron beam exposed and chromium line patterns were transferred on the Si surface via a lift-off process.     

Current status of large-area MOVPE growth of HgCdTe device heterostructures for infrared focal plane arrays

This paper reviews the current status of the growth of fully doped HgCdTe (MCT) devices by metalorganic vapor phase epitaxy (MOVPE). The current reactor system has been developed to produce 3-inch diameter epitaxial layers compatible with slice-scale processing. The new reactor system has achieved routine epitaxial growth of MCT with good morphology onto both gallium arsenide (GaAs) and GaAs on silicon (Si) wafers that were oriented (2–8°) off (100) orientation. The density of surface defects (so-called “hillocks”), typical of MOVPE growth on such orientation substrates, has been reduced to <5 cm⁻² at a sufficient yield to make the production of low cluster defect 2D arrays possible. Alternative growth experiments onto cadmium telluride (CdTe) on Si substrates with (211)B orientation have also been performed to investigate their usefulness for infrared focal plane array (IRFPA) applications. Si substrates give better thermal expansion match to the read out Si circuits (ROIC). The horizontal reactor cell design has a graphite susceptor with a rotating platen capable of using substrates up to 4-inch diameter. Work, however, has concentrated on 3-inch diameter GaAs and GaAs on Si wafers substrates in the reactor, and these reproducibly demonstrated good compositional and thickness uniformity. Cut-off wavelength and thickness uniformity maps showed that there was sufficient uniformity to produce twelve sites of large format 2D arrays (640×512 diodes on 24-μm pitch) per slice. Minority carrier lifetimes in heterostructures is an important parameter and some factors affecting this are discussed, with special emphasis on As-doped material grown under various growth conditions in an attempt to reduce Shockley-Read (S-R) trap densities. New data are presented on trap densities and theoretical fitting of lifetimes in MOVPE material. Fully doped heterostructures have been grown to investigate the device performance in the 3–5 μm medium-wave IR (MWIR) band and 8–12 μm long-wave IR (LWIR). These layers have been fabricated into mesa arrays and then indium-bumped onto Si multiplexers. A summary of the 80-K device results shows that state-of-the-art device performance has been demonstrated in MOVPE-grown device structures.     

The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications     

Thermal characterization of embedded electronic features by an integrated system of CCD thermography and self-adaptive numerical modeling

This work provides a practical application of a coupled experimental-computational system devised for the full characterization of the thermal behavior of complex three-dimensional active submicron electronic devices. A thermoreflectance thermography (TRTG) technique is used to non-invasively measure the 2D surface temperature field of an activated device, with submicron spatial resolution. The measured planar temperature distribution field is then used as input for an ultra-fast inverse computational solution to derive the three-dimensional temperature distribution throughout the device. For the purposes of this investigation, test micro-heater devices were constructed on epitaxial layers of natural (Si) and isotopically pure (Si²⁸) silicon. Then, all devices were activated and measured with the TRTG technique. In order to demonstrate the coupled experimental-computational system, the measured temperature fields of the samples whose thermal properties are known (Si) were used to extract critical physical parameters (the oxide layer thickness and the effective heater length). Then, since the devices with unknown thermal properties (Si²⁸) share the same construction with the Si devices, the extracted parameters were used together with the measured planar temperature fields to derive the thermal conductivity of Si²⁸. The extracted oxide layer thickness and thermal conductivity of Si²⁸ compared very closely to values obtained by other independent direct methods.     

In situ measurement of wafer temperatures in a low pressurechemical vapor deposition furnace

Axial and radial temperature profiles within the wafer load of a multiwafer LPCVD furnace were measured in situ using a pair of instrumented wafers. The measurements confirm that the wafer load is not in thermal equilibrium with the furnace tube, as has been widely assumed in many modeling studies. The measurements confirm temperature variations predicted previously from a study of polysilicon film thickness profiles. Temperature variations were small for wafers near the center of the 150-wafer load. However, axial variations of up to 25°C and radial variations of up to 5°C were measured at the extremes of the wafer load. For a representative polysilicon deposition data set, axial and radial thin-film thickness variations were found to correlate closely with measured temperature variations. The temperature profile was found to be insensitive to gas composition and flowrate, establishing radiation as the dominant mode of heat transfer. A pair of polysilicon coated quartz radiation shields was shown to improve polysilicon film thickness uniformity both down the load (along the furnace axis) and across each wafer     

Plasma charging defect characterization, inspection, and monitors in poly-buffered STI

In this paper, the mechanism, inspection, and inline monitor of plasma charging defects found in an active area (AA) corner and edge using a poly-buffer (PB) STI process is reported. These defects are formed by the arcing (or discharging) through weak spots of pad-oxide between the poly-buffer layer and substrate as resulting from the charging of poly buffer layer during reverse-AA oxide etching. Such defect formation is found to be strongly enhanced by the magnetic field used in oxide etchers but not related to etch rate and plasma density. The defect inspection on patterned wafers is found to be strongly correlated to the flat-band voltage (V/sub fb/) and to a lesser extent to oxide charge (Q/sub tot/) degradation on in-line unpatterned oxide wafers. Therefore, the shift of V/sub tb/ and Q/sub tot/ on unpatterned wafers can be effective inline monitors for plasma charging damage during reverse-AA etching in PB-STI process.     

Design Rules for Addressing Material Asymmetry Induced by Templated Epitaxy for Integrated Heteroepitaxial On-Chip Light Sources

Integrating quantum dot (QD) gain elements onto Si photonic platforms via direct epitaxial growth is the ultimate solution for realizing on-chip light sources. Tremendous improvements in device performance and reliability have been demonstrated in devices grown on planar Si substrates in the last few years. Recently, electrically pumped QD lasers deposited in narrow oxide pockets in a butt-coupled configuration and on-chip coupling have been realized on patterned Si photonic wafers. However, the device yield and reliability, which ultimately determines the scalability of such technology, are limited by material uniformity. Here, detailed analysis is performed, both experimentally and theoretically, on the material asymmetry induced by the pocket geometry and provides unambiguous evidence suggesting that all pockets should be aligned to the [1 $\overline{1}0$] direction of the III-V crystal for high yield, high performance, and scalable on-chip light sources at 300 mm scale.     

New OMVPE reactor for large area uniform deposition of InP and related alloys

The deposition uniformity in a chimney reactor, with a sidearm to accommodate sus-ceptor rotation and mechanized substrate loading, has been characterized by mapping the thickness of InP deposited on 50-mm-diam. GaAs substrates. Susceptor rotation im-proves the thickness uniformity by approximately a factor of seven, with the thickness uniformity reproducibly held to less than 3% across 40 mm, under typical growth con-ditions. The deposition pattern is independent of rotation rate from 3 to 120 rpm, which corroborates the existence of a slow-rotation regime (observed in an earlier flow visu-alization study) where susceptor rotation does not disturb the gas flow. In agreement with that interpretation, the observed deposition pattern with susceptor rotation is about the same as that predicted from a circular average of the results without rotation. Also, some discussion is given of growth parameters which influence the surface morphology of heteroepitaxial InP on GaAs.     

Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

Improvements of the SiC homoepitaxy process in a horizontal cold-wall CVD reactor

In this research effort, we investigate the influence of the cold-wall reactor geometry on the chemical vapor deposition (CVD) growth process of 4H-SiC and the quality of lightly doped epitaxial layers. Stable growth conditions with respect to growth rate and C/Si ratio of the gas-phase can be achieved by the appropriate choice of the distance between susceptor and walls of the inner quartz tube. A background doping concentration in the range of 10¹⁴ cm⁻³ is realized by employing a high temperature stable and hydrogen etch resistant coating of the graphite susceptor. Doping and thickness homogeneity of epitaxial layers on 35 mm diam. 4H-SiC substrates, expressed by σ/mean, are as low as 6.9 and 7.7%, respectively. From deep level transient spectroscopy measurements, the concentration of the frequently reported intrinsic Z₁-center in 4H-SiC is determined to be below the detection limit of 10¹² cm⁻³.