结合雪崩和PIN特性的4H-SiC紫外光电探测器的模拟

紫外波段的光探测器具有广阔的应用前景,本文结合传统的吸收-倍增-分离(SAM)和PIN结构,设计了一种新结构(APIN)的4H-Si C紫外光电探测器,模拟了其光电特性,并与传统的SAM和PIN结构的光电探测器进行了对比。结果表明其在雪崩状态下具有类似于SAM结构的雪崩光电探测器(APD)的特性,在低反向偏压下具有类似于PIN光电探测器的特性,为实际器件的制备提供参考。     

基于OrCad软件的PIN光电探测器的Pspice建模仿真分析

利用OrCad软件的Model Editor模块建立了PIN光电探测器的Pspice仿真模型,对比分析了PIN光电探测器的实验数据与仿真数据,对PIN光电探测器仿真模型进行修正.最终建立了可用于电路仿真的PIN光电探测器的Pspice模型,该模型有助于设计人员在工程设计之初,利用仿真软件对光电接收电路进行仿真优化.     

硅基PIN光电探测器的设计与模拟

介绍了单片集成硅光接收器的研究背景,阐述了硅光电探测器的工作机理.设计了一种应用于单片集成硅光接收器的PIN结构光电探测器,并用Silvaco软件对光电探测器的器件结构、光谱响应、响应电流及其随入射光功率的变化、器件的暗电流分别进行了模拟,对模拟结果进行了分析.设计了该光电探测器的版图,给出了其主要工艺流程,搭建了其光响应谱测试电路.最后对研究结果进行了总结.     

与CMOS工艺兼容的硅高速光电探测器模拟与设计

用器件模拟的方法,设计了一种与常规CMOS 工艺兼容的硅高速光电探测器,该探测器可与CMOS接收机电路单片集成,对该探测器进行了器件模拟研究,给出了该探测器的电路模型.通过MOSIS(MOS implementation support project) 0.35μm COMS工艺制做了该探测器,实际测试了该器件的频率响应和波长响应,探测器频率响应在1GHz以上,峰值波长响应在0.69μm.     

与CMOS工艺兼容的硅高速光电探测器模拟与设计

用器件模拟的方法,设计了一种与常规CMOS 工艺兼容的硅高速光电探测器,该探测器可与CMOS接收机电路单片集成,对该探测器进行了器件模拟研究,给出了该探测器的电路模型.通过MOSIS(MOS implementation support project) 0.35μm COMS工艺制做了该探测器,实际测试了该器件的频率响应和波长响应,探测器频率响应在1GHz以上,峰值波长响应在0.69μm.     

Si基PIN光电探测器电场隔离结构对暗电流的影响

对Si基PIN光电探测器的电场隔离结构进行了研究,讨论了电场隔离结构的作用以及其与暗电流的关系,并进行了仿真模拟与测试分析.电场隔离结构主要将有源区和边缘隔离从而降低暗电流,结合仿真模拟结果和实验测试结果,分析得到电场隔离结构主要降低与周长有关的暗电流,对于小尺寸器件作用更明显.     

超深亚微米SOI总剂量效应泄漏电流模型

总剂量辐射效应会导致绝缘体上硅金属氧化物半导体场效应晶体管(SOI MOSFET)器件的阈值电压漂移、泄漏电流增大等退化特性。浅沟槽隔离(STI)漏电是器件退化的主要因素,会形成漏极到源极的寄生晶体管。针对130 nm部分耗尽(PD) SOI NMOSFET器件的总剂量辐射退化特性,建立了一个包含总剂量辐射效应的通用模拟电路仿真器(SPICE)模型。在BSIM SOI标准工艺集约模型的基础上,增加了STI寄生晶体管泄漏电流模型,并考虑了辐射陷阱电荷引起寄生晶体管的等效栅宽和栅氧厚度的变化。通过与不同漏压下、不同宽长比的器件退化特性的实验结果对比,该模型能够准确反映器件辐射前后的漏电流特性变化,为器件的抗辐射设计提供参考依据。     

中红外GaInAsSb PIN多结光伏探测器设计与数值模拟

从非平衡载流子的扩散 -复合理论出发 ,提出 PIN多结探测器材料结构 ,并建立了理论模型进行定量计算 ,从理论上解决了不能同时兼顾增大量子效率与光电增益和降低噪声的矛盾。利用该模型对 Ga In As Sb材料体系作了数值模拟 ,单结器件性能的计算值和实测值基本吻合 ,并根据多结器件模拟结果设计了工作于2 .4μm波段的 Ga In As Sb PIN多结材料结构     

PIN四象限探测器输出特性的改进研究

PIN四象限探测器在应用过程中对其输出一致性的要求很高。文章讨论了影响PIN四象限探测器输出一致性的各种因素,并有针对性地提出了相应的改进措施。通过仿真分析,对PIN器件的各项参数进行了优化设计,并制作出了可工作在1 060nm波长、50V偏压下的PIN四象限探测器,其每个象限响应度达到0.3A/W,暗电流小于50nA,四个象限输出不一致性小于10%。然后通过对单个芯片的四个象限分别进行放大电路的安装调试,制作出了输出不一致性小于3%的四象限探测器器件。     

硅基PIN光电探测器结构参数对其性能的影响

对硅基PIN光电探测器器件模型进行了理论分析,讨论了硅基PIN光电探测器的I-V特性与器件的i层厚度和整体宽度的变化关系,并进行了仿真分析。实验结果表明,随着i层厚度从5μm增加到70μm,器件的正向电流逐步减小,且i层厚度与其正向电流成反比;随着器件宽度从50μm增加到90μm,器件的正向电流逐步增大,且器件宽度与其正向电流成正比;引入保护环结构可以明显降低器件的暗电流。对PIN器件的结构参数进行了优化设计,结果表明在所设置的器件工艺条件下,当器件的i层厚度为50μm、整体宽度为70μm时,器件的性能最佳。     

Small Signal Circuit Model of Double Photodiodes

The transmission delay of photogenerated carriers in a CMOS- process- compatible double photodiode (DPD) is analyzed by using device simulation. The DPD small signal equivalent circuit model which includes transmission delay of photogenerated carriers is given. From analysis on the frequency domain of the circuit model the device has two poles. One has the relationship with junction capacitance and the DPD‘s load, the other with the depth and the doping concentration of the N-well in the DPD. Different depth of the Nwell and different area of the DPDs with bandwidth were compared. The analysis results are important to design the high speed DPDs.     

Modeling and simulation of insulated-gate field-effect transistor switching circuits

A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET memory cell.     

Equivalent Circuit Modeling of Separate Absorption Grading Charge Multiplication Avalanche Photodiode

In this paper, a novel equivalent circuit model for the frequency performance of separate absorption grading charge multiplication (SAGCM) avalanche photodiode (APD) is developed. This model includes effects of carrier transit time, avalanche buildup time, and parasitic RC elements. Based on the equivalent circuit model, frequency and bandwidth characteristics of SAGCM APD can be simulated in advance to device fabrication, and the simulation results are in good agreement with experimental data. Conventional pin photodiodes can also be simulated as a special case when M=1. In addition, the frequency response of SAGCM APDs and pin photodiodes with different illumination directions are investigated.     

Equivalent circuit model for a THz detector based on the double-electron layer tunneling transistor (DELTT)

An equivalent circuit model for the double-electron layer tunneling transistor (DELTT) integrated with an antenna is presented in this paper. This device is used basically for THz detection, and the antenna is used to efficiently couple THz radiation into the device for processing. Developing an equivalent circuit model is extremely helpful in matching the antenna to the device.     

An improved GaAs device model for the simulation of analog integrated circuit

This paper describes an improved device model of GaAs MESFETs and heterojunction FETs for the design and analysis of analog integrated circuits. The proposed device model provides a new expression for the current and the capacitance of the device,which gives excellent agreements with experimental data for all regions of device operation. For the expression of the low frequency anomalies of GaAs devices, an improved technique with an equivalent circuit are presented to model the frequency dispersion of the transconductance and the drain conductance of the device, which give a good agreement with the experimental data of both the frequency dispersion and the lag effect of the device. The new device model proposed here clearly provides a superior prediction of the performance of GaAs analog integrated circuit.     

An improved multipeak resonant tunneling diode model for nine-stateresonant tunneling diode memory circuit simulation

A simple Spice equivalent circuit model for simulating current-voltage (I-V) characteristics and logic operation waveforms of an eight-peak resonant tunneling diode is presented. The simulated results agreed well with experimental data measured from an eight-peak resonant tunneling diode device fabricated by Seabaugh's experiment. This is shown through PSpice simulation     

Intrinsic stability of an HBT based on a small signal equivalent circuit model

Intrinsic stability of the heterojunction bipolar transistor(HBT) was analyzed and discussed based on a small signal equivalent circuit model.The stability factor of the HBT device was derived based on a compact T-type small signal equivalent circuit model of the HBT.The effect of the mainly small signal model parameters of the HBT on the stability of the HBT was thoroughly examined.The discipline of parameter optimum to improve the intrinsic stability of the HBT was achieved.The theoretic analysis resul...     

基于小信号等效电路模型的HBT本征稳定性研究

本文基于小信号等效电路模型,对异质结双极晶体管的本征稳定性进行了分析和讨论。稳定性因子（即K因子）用于评估器件的高频稳定特性。基于HBT的T型等效电路模型,推导了K因子的理论分析公式,并全面分析了小信号模型中物理参数对器件本征稳定性的影响,得到了提高器件本征稳定性的物理参数优化设计方法。测试计算了多个不同物理参数的HBT样品的稳定性因子K。物理参数对器件稳定性影响的实验结果与理论分析的影响规律一致。     

Interpretation of the static and dynamic characteristics of 1-Dthin film position sensitive detectors based on a-Si:H p-i-n diodes

In this work, we present a model to interpret the steady-state and the dynamic detection limits of 1-D Thin Film Position Sensitive Detectors (1-D TFPSD) based on p-i-n a-Si:H devices. From this, an equivalent electric circuit is derived and the predicted values are compared with the experimental results obtained in 1-D TFPSD devices, with different sizes. The model is also able to determine the device characteristics that influence the spatial limits and the response time of the device     

An analysis and experimental investigation of the binistor

This article is an analysis of a four-layer semiconductor device known as the binistor. An approximate equivalent of this device may be constructed from suitably connected NPN and PNP transistors. Analysis of the equivalent circuit configuration by means of the small-signal hybrid parameters enables a prediction of the circuit characteristics. From this analysis, it is shown that the device exhibits a voltage-stable negative-resistance characteristic in contrast with the usual current-stable negative resistance obtained from circuits employing a four-layer semiconductor device. This analysis indicates the manner in which the negative-resistance portion of the collector current-voltage characteristic is dependent upon the small-signal parameters of the NPN and PNP transistors and upon a certain resistance external to the device. A linear model of the device is proposed. Use of the model allows a prediction, within experimental accuracy, of the switching characteristics of the binistor used as a bistable device. Switching between the two states may be accomplished by three methods of control. This model suggests that the transfer characteristic between two particular ports should have the hysteresis characteristics of a mechanical relay. This analysis is born out by experiment. A circuit formed by a series combination of two binistors is shown. This circuit has two stable states with a stable output either at essentially the supply voltage, or at approximately ground potential. A modification with an intermediate stable state is also obtainable with the proper bias conditions. A logical extension of the binistor structure to a device that may have any desired number of stable states is proposed and a circuit of this type with three stable states is shown and discussed. Because of certain internal interaction phenomena, the device may be used as a modulator, and an experimental modulator circuit is developed and investigated.