分割单元对电源/地平面输入阻抗影响的研究

研究了在多层印制电路板电源/地平面过孔周围布置具有桥接结构的蚀刻分割单元时过孔信号的返回路径阻抗及转移阻抗。分析了分割单元尺寸变化对返回路径阻抗的影响。采用二维边界元法进行了数值分析,并通过全波有限元分析软件进行了仿真验证。研究结果表明,在频率较高时,分割单元会激发较多的谐振峰值,返回路径阻抗大幅上升,但有助于降低噪声耦合。     

多层PCB 电源地平面返回路径阻抗的边界元分析

研究了多层印制电路板(PCB)中含有一个信号过孔的电源/地平面返回路径阻抗的频域特性,并分析采用添加短路过孔的方法减小多层PCB的输入阻抗.电源/地平面形成了径向传输线结构,反焊盘处的输入阻抗即为信号电流在电源/地平面间的返回路径阻抗.在电源/地平面外部边界施加PMC(完全导磁体)边界条件,在反焊盘处施加电流激励源,短路过孔轴向电场为零,采用高效的二维边界元法求解.计算了10GHz内电源/地平面返回路径的输入阻抗.结果表明:在两特性相同的平面之间添加短路孔可以降低输入阻抗,同时,电源、地平面的输入阻抗随频率变化交替呈现容性或感性,在反谐振频率处输入阻抗值可达几百欧姆,此外,在频率较低时输入阻抗可用静态电容或静态电感表示.采用基于全波分析的有限元软件验证了计算结果和计算方法的正确性.     

电流返回路径分解的信号完整性分析方法

提出了一种适用于高速互连电路的信号完整性快速仿真方法。根据电流返回路径 不同,该方法将有过孔的三维互连结构分解为电源平面对阻抗模型和微带线模型,先单独分 析两种模型特性,再级联以求解整个互连结构特性。与全波仿真方法相比,本方法在保证准 确度的前提下可将仿真时间从95 min降低至1 min以内。分析了电路板参数、去耦电容和短 路孔对信号完整性的影响,结果表明插入损耗由电源平面结构在过孔位置处的自阻抗决定。 在工程设计中,可采用减小电源平面对结构厚度、添加去耦电容和选择适当的过孔位置等方 法提高信号完整性     

介质型EBG结构对同步开关噪声抑制的有限元分析

研究了介质型电磁带隙结构对高速电路中电源/ 地平面间同步开关噪声的抑制作用。该介质型电磁带隙结构在抑制同步开关噪声的同时未破坏高速信号的电流返回路径,使高速信号的信号完整性得以保持。利用电磁场有限元方法将电源/地平面间同步开关噪声抑制的三维问题转化成二维问题进行处理,提高了计算效率。分析了介质型电磁带隙结构的介电常数对噪声抑制带宽的影响,利用了三维全波电磁场仿真软件HFSS对二维数值结 果进行仿真验证,仿真结果与数值计算结果基本吻合,验证了二维数值算法的正确性。     

2008 IEEE EMC学术研讨会——第三部分PCB设计

Noise Coupling between Signal and Power/Ground Nets due to Signal Vias Transitioning through Power/Ground Plane Pair 摘要：PCB板上的信号过孔通常会穿过电源层和地层，引起串扰。本文通过分割法，结合过孔电容模型和电源／地夹层腔体模型对噪声耦合机制进行了研究。 关键词：信号传输过孔；分割法；电源／地节点视点：分割法的原理与运用     

多层PCB介质基板中嵌入高K材料对信号完整性的影响

采用数值仿真分析了多层PCB的电源/地平面中嵌入高K材料对过孔转换信号完整性的影响。研究了电源/地平面间的介质层整体采用高介电常数(高K)材料时信号过孔的S参数,并提出了两种局部添加高K材料的方法,一是在过孔周围布置一个包围过孔的介质柱,二是在过孔周围均匀布置若干个小介质柱。计算结果表明,介质层整体采用高K材料会引起较多的谐振,信号完整性变差;当嵌入介质材料的介电常数足够大时,在过孔周围局部嵌入高K材料的方法可明显增强信号完整性,其中,包围过孔的单个介质柱在高频时的性能良好,而在过孔周围嵌入多个小介质柱在低频时的效果较好。     

高速差分过孔的仿真分析

高速差分信号传输中也存在着信号完整性问题。差分过孔在频率很高的时候会明显地影响差分信号的完整性,现介绍差分过孔的等效RLC模型,在HFSS中建立了差分过孔仿真模型并分析了过孔尤其过孔长度对信号完整性的影响。     

高速电路中地弹噪声抑制的研究

研究了高速电路领域中的一类重要的电源完整性问题,即电源地平面之间激发的地弹噪声问题。地 弹噪声的存在严重破坏了电源/ 地平面的完整性,导致供电电压幅度的不稳定,严重之时甚至导致电路的误判。针 对这一问题,设计了一种超宽带电磁带隙结构。实验结果表明,这种电磁带隙结构可以在0. 5 ~5. 5GHz(11 倍频程) 频段内实现优于30dB 的噪声抑制能力。文章还探讨了带隙结构作为电源平面时信号传输的完整性。研究表明,如 果电路工作频率高达GHz 或更高,在电源/ 地平面采用这种带隙结构,可以有效地避免地弹噪声带来的影响,并保证 电源和信号的完整性。     

一种适用于超宽带通信的微带垂直转换结构

该文提出一种适用于超宽带电路的基于过孔的微带垂直转换结构。通过在过孔附近的电源层上蚀刻平面电磁带隙单元来抑制电源分配网络谐振,降低其在过孔处的自阻抗,以改善垂直互连结构传输性能。将互连结构分解为过孔处耦合的微带线结构和电源平面对结构,并使用网络分析方法快速估算系统传输性能。仿真和实验测试表明,在3.1-10.6 GHz的超宽带频段内过孔的插入损耗小于0.4 dB。与在电源分配网络之间添加短路过孔方法相比,该结构在传输性能相当的前提下减少了一个布线层,从而降低了设备成本。     

高速BGA封装与PCB差分互连结构的设计与优化

随着电子系统通信速率的不断提升,BGA封装与PCB互连区域的信号完整性问题越来越突出。针对高速BGA封装与PCB差分互连结构进行设计与优化,着重分析封装与PCB互连区域差分布线方式,信号布局方式,信号孔/地孔比,布线层与过孔残桩这四个方面对高速差分信号传输性能和串扰的具体影响。利用全波电磁场仿真软件CST建立3D仿真模型,最后时频域仿真验证了所述的优化方法能够有效改善高速差分信号传输性能,减小信号间串扰,实现更好的信号隔离。     

改进的二维三维混合时域不连续伽辽金方法

对高速信号通过电源板时的电源完整性(power integrity, PI)问题进行研究时, 因为电源板中主要模式分布为零阶平行板模式, 可以采用二维简化以提高效率.而对于隔离盘或其它存在纵向不连续性的区域, 则应采用三维算法以保证精度.将两者结合起来的一种二维三维(2D/3D)混合时域不连续伽辽金(discontinuous Galerkin time domain, DGTD)方法可以兼顾精度与效率, 有效地处理这类电磁全波计算问题.其中二维、三维方法采用同一套三棱柱离散的网格, 通过适当设置基函数, 二维区域与二维区域之间可以方便快速地相互转化.随着电磁波的传播, 二维、三维的适用区域是随时间、空间动态变化的.为了准确地捕捉这种动态变化, 文中提出的一种改进的自适应判据, 在每个时间歩对电磁场进行检测, 从而动态地判定二维简化区域.与现有技术的判据控制绝对误差不同, 该方法对相对误差进行控制, 效率高、精度好, 对于不同的结构适应性强.通过数值实验, 与商业软件和全三维(3D)DGTD方法的结果进行了比较和验证.     

A Semi-Analytical Approach for System-Level Electrical Modeling of Electronic Packages With Large Number of Vias

This paper presents a semi-analytical approach for electrical performance modeling of complex electronic packages with multiple power/ground planes and large number of vias. The method is based on the modal expansion technique and the method of moments. For the inner package domain with multiple power/ground planes and many vias, the modal expansion method is employed to compute the electromagnetic fields from which the multiport network parameters, e.g., the admittance matrix can be easily obtained. For the top/bottom domain of signal layers, the moment method is used to extract the equivalent resistance, inductance, capacitance, and conductance (RLCG) parameters. The equivalent circuit for the entire package is then generated by combining the results for both package domains. The equivalent circuit can be used in a SPICE-like simulator to study the signal and power integrity of an electronic package. Numerical examples demonstrate that the new approach is able to provide fast yet accurate signal and power integrity analysis of multilayered electronic packages.     

Fast analysis of bounces on power/ground planes using even-odd partition

A novel method for analyzing the bounces on structure of parallel power/ground planes by using the even-odd mode partition is presented in this paper. Based on the distributed RLCG circuit model derived from the two dimensional electromagnetic field equations of the power/ground planar structure, this method can speed up the circuit simulation of the bounces on power/ground planes by using even-odd mode partition. Furthermore, the method can be used to evaluate the effects of the terminated decoupling capacitors and the hole structures on power/ground plane. The numerical examples demonstrate that the method has both high efficiency and good precision.     

基于EBG结构的新型超宽带低噪声电源/地平面设计

将电磁带隙（EBG）结构加载在电源/地平面之间,依据理论分析对模型结构以及各项参数进行优化.设计出抑制深度为-80 dB、禁带宽度为10 GHz的超宽禁带电源/地平面,在拥有优良抑制电磁干扰能力的同时,也保证了信号的完整性.在禁带内,该平面可以有效地抑制电路之间特别是共用电源/地平面的数字电路与射频电路之间所引起的电磁干扰.仿真实验表明,该设计取得了理想的效果.     

Time-domain approach for synthesising SPICE-compatible models of power delivery networks of printed circuit board

Resonance noise, or power/ground bounce noise, between the power and ground planes of high-speed circuit packages is one of the main concerns of signal integrity or power integrity issues. A novel time-domain approach is proposed to extract the equivalent circuit models of power/ground planes by time-domain reflection and time-domain transmission waveforms. The extracted model can accurately predict the resonance behaviour of power/ground planes over a wide frequency range. These models can be efficiently incorporated into the HSPICE simulator for the consideration of power/ground bouncing noise in high-speed circuits.     

A novel power plane with super-wideband elimination of ground bounce noise on high speed circuits

A novel L-bridged electromagnetic bandgap (EBG) power/ground planes is proposed with super-wideband suppression of the ground bounce noise (GBN) from 600Mz to 4.6GHz. The L-shaped bridge design on the EBG power plane not only broadens the stopband bandwidth, but also can increase the mutual coupling between the adjacent EBG cells by significantly decreasing the gap between the cells. It is found the small gap design can prevent from the severe degradation of the signal quality for the high-speed signal referring to the perforated EBG power plane. The excellent GBN suppression performance with keeping reasonably good signal integrity for the proposed structure is validated both experimentally and numerically. Good agreement is seen.     

Parasitic modes on printed circuit boards and their effects on EMCand signal integrity

In this paper, parasitic modes, such as slotline, parallel plane, and surface wave (SW) modes, commonly found on printed circuit boards (PCBs) are analyzed and their effects on electromagnetic compatibility (EMC) and signal integrity are discussed. The analysis is based on numerical simulations using the finite difference time domain (FDTD) method which is shown to be very well suited for rigorous modeling of parasitic mode effects. The EMC and signal integrity problems discussed include power loss, crosstalk, ground bounce, and free space radiation. Design guidelines for improved EMC and signal integrity are derived from the results obtained. Comprehensive simulation and characterization of SWs using FDTD is presented for the first time