ESD防护器件中SCR结构开启速度的优化与分析

针对静电放电(ESD)防护过程中ESD防护器件开启速度慢、易引起栅氧击穿或电路烧毁的问题,提出了一种可控硅(SCR)结构的ESD防护器件开启速度的优化方法。首先,基于0.35μm Bipolar-CMOS-DMOS(BCD)工艺制备了P~+浮空和P~+接地SCR结构器件,通过分析阱间距对P~+接地SCR影响,获知当阱间距增至8.68μm时,器件开启速度快且过击穿电压低。其次,对比分析关键尺寸参数相同条件下P~+接地与P~+浮空SCR器件ESD防护性能,传输线脉冲测试结果表明,P~+浮空比P~+接地SCR开启速度更快。最后,通过进一步优化P~+浮空SCR器件特征参数,器件开启速度可提高约17.70%。TCAD仿真结果证明:与P~+接地SCR相比,P~+浮空SCR的电流密度分布较均匀,且导通时间短,有利于提高开启速度,因此P~+浮空SCR器件更适用于高速集成电路的ESD防护。     

应用于片上ESD防护中新式直通型MOS触发SCR器件的研究

在基于0.13μm CMOS工艺制程下,为研究片上集成电路ESD保护,对新式直通型MOS触发SCR器件和传统非直通型MOS触发SCR进行了流片验证,并对该结构各类特性进行了具体研究分析。实验采用TLP(传输线脉冲)对两类器件进行测试验证,发现新式直通型MOS触发SCR结构要比传统非直通型MOS触发SCR具有更低的触发电压、更小的导通电阻、更好的开启效率以及更高的失效电流。     

基于高分子电压诱导变阻膜的全PCB抗脉冲防护

随着芯片集成度的不断提高,内部互连导线间距越来越小,器件更易在静电作用下受到损害。为提高印制电路板（PCB）在实际应用中抗静电放电（ESD）和电磁脉冲（EMP）的能力,制作了一种高分子电压诱导变阻膜,将其嵌入PCB中形成脉冲吸收网络,使全板具备抗瞬变脉冲能力,实现对ESD和EMP的全系统防护。ESD防护实测结果表明,对比普通PCB,全抗脉冲PCB对静电脉冲有更快的响应速度和更高的释放效率;传输线脉冲（TLP）测试结果表明,采用电压诱导变阻膜的PCB中每一点都具有过电压脉冲吸收能力,电流泄放能力可达50 A以上。     

一种具有n型隐埋载流子存储层的BRT新结构

提出了一种具有n型隐埋载流子存储层的基极电阻控制晶闸管（BRT）新结构。利用TCAD仿真软件对其工作机理和静态特性进行了分析，并与双栅BRT进行了性能对比。结果表明，新器件导通时会产生电子注入增强效应，由绝缘栅双极晶体管模式快速转换成晶闸管模式，当n型隐埋层浓度为8×1015 cm-3，隐埋层与p基区相接并与p++分流区距离接近时，能够有效抑制器件中的电压折回现象，获得良好的导通特性。新器件的导通压降为3.84 V，比传统器件减少了26%。     

0.18μm混合信号RFCMOS工艺中新型低触发电压双向SCR静电防护器件的设计

提出了一类新型片上SCR静电放电防护器件,此类器件用于保护芯片双向抗击静电应力.比较和分析了四种双向SCR器件的触发电压.其中采用嵌入pMOS管或nMOS管的双向SCR器件结构具有可调触发电压,低漏电流（~pA）和开启速度快的骤回I-V特性,并且没有闩锁问题.该器件的抗ESD能力可达~94V/μm.此类新型ESD防护器件具有面积小、寄生效应小的特点.     

用于ESD防护的PDSOI NMOS器件高温特性

研究了基于0.18μm部分耗尽型绝缘体上硅(PDSOI)工艺的静电放电(ESD)防护NMOS器件的高温特性。借助传输线脉冲(TLP)测试系统对该ESD防护器件在30~195℃内的ESD防护特性进行了测试。讨论了温度对ESD特征参数的影响,发现随着温度升高,该ESD防护器件的一次击穿电压和维持电压均降低约11%,失效电流也降低近9.1%,并通过对器件体电阻、源-体结开启电压、沟道电流、寄生双极结型晶体管(BJT)的增益以及电流热效应的分析,解释了ESD特征参数发生上述变化的原因。研究结果为应用于高温电路的ESD防护器件的设计与开发提供了有效参考。     

ESD与EMP对微波晶体管损伤机理研究

主要论述了电子装备中易受静电放电(ESD)和电磁脉冲(EMP)损伤的微波半导体器件的失效模式和失效机理.实验与理论分析结果表明,电流放大系数hFE是ESD、EMP损伤的敏感参数;在ESD、EMP的作用下,器件进入雪崩击穿状态(反偏注入),从而诱发热电子注入效应,使hFE逐渐退化;BC结反偏时的失效能量低于EB结反偏时的失效能量,BC结是EMP损伤的较易损端口;改进器件的结构设计、提高器件抗ESD、EMP能量,可有效提高电子装备抗电磁脉冲的可靠性水平.     

一种用于高压防护的新型闩锁免疫LDMOS

横向双扩散MOSFET(LDMOS)由于其高击穿电压特性而被认为是适合在高压中应用的防止静电放电(ESD)现象的保护器件.在传统结构中,LDMOS的鲁棒性相对较差,这是器件自身固有的不均匀导通特性和Kirk效应导致的.可将可控硅整流器(SCR)嵌入到LDMOS结构(即NPN_LDMOS)中.然而,SCR固有的正反馈效应...     

一种新型双Fin ESD防护单元研究

为满足小尺寸器件的ESD防护需求，基于Fin技术，提出了一种具有寄生SCR的STI双Fin结构。通过采用双Fin布局和深掺杂技术，减小了器件的基区宽度，避免了Fin技术中由弱电导调制导致的SCR无法开启的现象。仿真结果表明，相比于DFSD结构，新结构失效电流I_t2/Wlayout从21.67 mA/μm增加到28.33 mA/μm;触发电压V_t1从14.08 V减小到9.64 V。在ESD来临时，新结构能够实现有效的开启，泄放大电流。     

0.18μm混合信号RFCMOS工艺中新型低触发电压双向SCR静电防护器件的设计

提出了一类新型片上SCR静电放电防护器件,此类器件用于保护芯片双向抗击静电应力.比较和分析了四种双向SCR器件的触发电压.其中采用嵌入pMOS管或nMOS管的双向SCR器件结构具有可调触发电压,低漏电流(～pA)和开启速度快的骤回Ⅰ-Ⅴ特性,并且没有闭锁问题.该器件的抗ESD能力可达～94V/μm.此类新型ESD防护器件具有面积小、寄生效应小的特点.     

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-/spl mu/m CMOS process

The turn-on mechanism of a silicon-controlled rectifier (SCR) device is essentially a current triggering event. While a current is applied to the base or substrate of the SCR device, it can be quickly triggered into its latching state. In this paper, a novel design concept to turn on the SCR device by applying the substrate-triggered technique is first proposed for effective on-chip electrostatic discharge (ESD) protection. This novel substrate-triggered SCR device has the advantages of controllable switching voltage and adjustable holding voltage and is compatible with general CMOS processes without extra process modification such as the silicide-blocking mask and ESD implantation. Moreover, the substrate-triggered SCR devices can be stacked in ESD protection circuits to avoid the transient-induced latch-up issue. The turn-on time of the proposed substrate-triggered SCR devices can be reduced from 27.4 to 7.8 ns by the substrate-triggering technique. The substrate-triggered SCR device with a small active area of only 20 /spl mu/m /spl times/ 20 /spl mu/m can sustain the HBM ESD stress of 6.5 kV in a fully silicided 0.25-/spl mu/m CMOS process.     

Design of SCR‐Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp

In this paper, MOS‐triggered silicon‐controlled rectifier (SCR)–based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR‐based ESD protection circuits with floating diffusion regions for inverter and light‐emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded‐gate NMOS (ggNMOS) in the MOS‐triggered SCR‐based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P‐well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the floating diffusion region. The trigger voltage was improved by the partial insertion of a P‐body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low‐ and high‐voltage applications were designed using 0.18 µm Bipolar‐CMOS‐DMOS technology, with 100 µm width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS‐6008).     

0.18μm RF CMOS双向可控硅ESD防护器件的研究(英文)

基于传统双向可控硅(DDSCR)提出了两种静电放电(ESD)保护器件,可应对正、负ESD应力从而在2个方向上对电路进行保护。传统的DDSCR通过N-well与P-well之间的雪崩击穿来触发,而提出的新器件则通过嵌入的NMOS/PMOS来改变触发机制、降低触发电压。两种改进结构均在0.18μmRFCMOS下进行流片,并使用传输线脉冲测试系统进行测试。实验数据表明,这两种新器件具有低触发电压、低漏电流(～nA),抗ESD能力均超过人体模型2kV,同时具有较高的维持电压(均超过3.3V),可保证其可靠地用于1.8V、3.3V I/O端口而避免出现闩锁问题。     

High dI/dT light-triggered thyristors

Directly light-triggered, 4000- and 6000-V thyristors were designed, fabricated, and tested to obtain high performance in dI/dt, dV/dt, and photosensitivity. Built-in resistors protected both auxiliary stages during high dI/dt turn-on. The novel use of etched moats to define the resistors was compatible with an optical gate structure that gives high dV/dt and good photosensitivity. No additional processing steps were needed to fabricate these devices, as compared to standard light-triggered thyristors. A record value of 1000 A/µs at 60 Hz was measured on a 6000-V thyristor, and 850 A/µs was safely triggered with only 1.8 mW of light. The dV/dt immunity of the photogate structure measured 4000 V/µs, rising exponentially to 80 percent of 4000 V, VDRM. Thyristors triggered by dV/dt were not destroyed. A new model of resistor heating was combined with the first measurements of the current pulses through both built-in resistors to identify the mechanism responsible for occasional burn-out of the second resistor. The failure mechanism was conductivity modulation in the surface of the resistor during its microsecond on-time caused by thermally generated carriers. The test results confirmed the utility of built-in resistors for high dI/dt performance with minimal light power and for nondestructive dV/dt triggering.     

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.     

Effect of illumination on noise and some other characteristics of p-n junctions in InSb

Spectra of low-frequency (f = 20 Hz-20 kHz) noise in InSb p-n junctions are investigated at different voltage biases and under different illumination intensities at T = 77°K.

It is found that fluctuations of ohmic leakage current are the main source of the current noise in the dark. Fluctuations of conduction of the space charge region (SCR) are observed only at sufficiently large forward biases. Under illumination fluctuations of the photocurrent make the essential contribution to the excess noises. It is shown that these fluctuations are generated in SCR and their peculiarities depend not only on the value of voltage bias but also on the level of illumination L. A variety of other characteristics of p-n junction are found to be conditioned by illumination level as well: with increasing L the photoelectric efficiency of the diode decreases, and an increase takes place in the equivalent differential conductivity of SCR as well as in the forward current measured at constant voltage biases on the p-n junction. Such changes may be explained either by a decrease of the carrier life-time in SCR or by an increase of the width of SCR.

Arguments are adduced supporting the supposition that excess fluctuations of conductivity of SCR arise only in some regions of SCR which are characterized by the specific mechanism of current conduction.     

Holding voltage investigation of advanced SCR-based protection structures for CMOS technology

A new silicon-controlled rectifier low voltage triggered (SCR-LVT), to be adopted as protection structure against electrostatic discharge (ESD) events, has been developed and characterized. A high holding voltage has been obtained thanks to the insertion of two parasitic bipolar transistors, achieved adding a n-buried region to a conventional SCR structure. These two parasitic transistors partially destroy the loop feedback gain of the two main npn and pnp BJTs, resulting in an increase of the sustaining (holding) voltage during the ESD event. A strong dependence of the holding voltage with the ESD pulse width has also been observed, caused by self-heating effects. 2D-device simulations (DESSIS Synopsys) have been performed obtaining results that perfectly fit the measurements over a wide temperature range (25 °C − 125 °C). Using device simulation results, the factors that influence the holding voltage, in terms of temperature dependence, but also in the behavior of the parasitic BJTs, are explained. A guideline to change the SCR holding voltage, related to the SCR design layout without any change to process parameters, is also proposed.     

A gate-coupled PTLSCR/NTLSCR ESD protection circuit fordeep-submicron low-voltage CMOS ICs

A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit     

ESD circuit model based protection network optimisation for extended-voltage NMOS drivers

New snapback circuit models for drain extended MOS (DEMOS) and complementary DEMOS-SCR structures used for ESD protection in high-voltage tolerant applications have been developed. The models were experimentally validated in a standard 0.35 μm CMOS process which requires 20 V compatible structures. It is shown that the new ESD models provide accurate representation of the structure breakdown, turn-on behaviour into conductivity modulation mode and dV/dt triggering effect, both in static and ESD transient conditions. A major application of this model is for initial ESD optimisation of complex mixed voltage analog circuits.