用于胚胎电子阵列的实验系统

胚胎电子阵列是新兴的研究方向,基于胚胎电子阵列实现的电路具有与生物类似的自修复、自组织等能力。当前研究多限于软件仿真,缺少相应的实验系统。设计了实验系统体系框架和电子细胞模拟模块结构并进行了实现,多块细胞模拟模块组成胚胎电子阵列,与外围的信号发生器、逻辑分析仪等仪器连接,构成胚胎电子阵列的实验系统。基于该实验系统进行了某胚胎电子阵列上目标电路的实现,实验表明,实验系统能够验证胚胎电子阵列功能,并能够监测阵列中关键信号,为研究阵列结构及自修复机制提供了硬件实验条件,具有很大的实际意义。     

总线胚胎电子细胞阵列中空闲细胞数目优选

胚胎仿生硬件技术为高可靠性大规模集成电路系统设计提供了一种新思路.在确定规模的总线胚胎电子细胞阵列中，为兼顾阵列的硬件资源消耗和可靠性，本文提出了一种阵列内空闲细胞数目的优选方法.基于多态系统可靠性理论，利用通用生成函数建立阵列的可靠性模型.以阵列MOS（Metal Oxide Semiconductor）管消耗数目为硬件资源消耗衡量指标，建立阵列的硬件资源消耗模型.基于阵列的可靠性和硬件资源消耗模型，在一定设计约束条件下，对阵列内空闲细胞数目进行优选.仿真实验和分析表明，该方法能够根据阵列设计要求选择最合适的阵列内空闲细胞数目，同时，解决了胚胎电子细胞阵列中空闲细胞数目选择依靠经验的问题.     

一种LUT型胚胎电子阵列的功能分化方法

针对LUT型胚胎电子阵列功能分化方法的不足,提出了一种新型的LUT型胚胎电子阵列功能分化方法,根据目标电路的功能描述,通过前端综合、逻辑优化、逻辑映射、打包等操作,将目标电路转换为电子细胞为基本节点的电路形式,通过物理映射、基因库生成,将电路映射到阵列上,确定阵列中每个细胞的功能、连接,最终生成目标电路的基因库并确定每个细胞的表达基因,完成胚胎电子阵列的功能分化.该方法无需对计算过程中每一代电路进行功能评估,运算量小,计算速度快,为基于LUT型胚胎电子阵列的自修复电路应用提供了设计方法.最后,使用一个算例阐述了功能分化过程,并通过多个电路验证了该方法的分化速度.     

一种新型仿生硬件容错系统——胚胎电子系统

本文介绍了一种从自然界获取灵感的新型容错设计方法--胚胎电子系统设计.它的容错原理是根据在生物细胞内部冗余结构里发现的自修复机制来实现的.胚胎电子系统,就是基于构造一个具有自检测和自修复能力的处理单元阵列的仿生硬件容错系统.本文阐述了这种容错方法的设计原理,介绍了该系统的基本结构,并通过一个设计实例的介绍来验证该方法的有效性.     

仿生容错系统的可靠性分析

人工生命科学就是研究生物机体的特征，胚胎电子学介绍了新一代生物灵感容错FPGA系列，适合于人工生命的研究，胚胎电子阵列通过硬件冗余和阵列重构机构获得容错功能，本文论述和分析了根据κ-out-of-m可靠性模型的胚胎电子阵列的重构策略。讨论了行取消和细胞取消两种方案。     

具有自修复能力的数字电路实现平台

胚胎型仿生硬件自提出以来已取得很大的研究进展,但偏重理论研究,与实际应用还有一定的差距。从工程应用的角度出发,详细介绍了如何设计一个基于电子细胞阵列的平台来实现具有自修复能力的数字电路。首先,对作为实现平台的细胞阵列结构进行简要的介绍,然后对阵列中电子细胞内的关键模块进行详细分析和具体设计,并以一个简单的数字电路为例说明了以上设计的合理性、可行性及通用性。     

胚胎阵列在容错系统中的应用

为了减少系统资源的占用量，对胚胎阵列的细胞结构进行改进。通过只在细胞中存储它们可能用到的信息来减少资源的占用率，以现场可编程门阵列（Field Programmable Gate Array，FPGA）为平台，验证了改进后胚胎阵列的可实现性，同时结果显示改进后的胚胎阵列在资源利用方面更具优势。     

基于单电子晶体管细胞神经网络的实现方法

基于单电子晶体管(SET)的I-V特性和CNN细胞单元的硬件结构原理，给出了三种基于SET的CNN硬件电路具体实现方法：一是基于SET的库仑振荡特性和CMOS数字电路的设计思想方法；二是根据细胞单元的等效结构分块实现方法；三是基于SET阵列的传输特性实现CNN方法，并重点阐述了后两种SET的CNN实现方法，分析了它们的优缺点。     

微型多道成像光谱探测列阵的设计

介绍一种新颖的微型多道成像光谱分析系统用的控制列陈。通过对探测器工作原理分析，电路及传感器元件结构的优化设计，研制出５１２位象元自扫描光电二极管阵列的２００ｎｍ－１０００ｎｍ宽米谱响应的探测器，并给出了实验结果。     

一种新型的仿生电子细胞基因存储结构

基因存储是电子细胞的重要组成部分,已有的基因存储无法兼顾系统的可靠性和硬件消耗。设计了一种新型的基因存储结构,细胞采用相关冗余方式存储系统的部分基因。通过基因更新过程,基于相邻细胞的基因信息恢复故障细胞损失的基因。细胞内存储基因数目与阵列和目标电路规模无关,可由设计者根据系统需求设置。理论分析和仿真实验表明,该基因存储不仅实现了阵列功能分化和自修复,而且可在保持系统可靠性的前提下,降低基因存储的硬件消耗,可用于大规模仿生自修复芯片的设计。     

Embryonics: a new methodology for designing field-programmable gatearrays with self-repair and self-replicating properties

The growth and the operation of all living beings are directed through the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the conception of very large scale integrated circuits endowed with properties usually associated with the living world: self-repair (cicatrization) and self-replication. We begin by showing that any logic system can be represented by an ordered binary decision diagram (OBDD), and then embedded into a fine-grained field-programmable gate array (FPGA) whose basic cell is a multiplexer with programmable connections. The cellular array thus obtained is perfectly homogeneous: the function of each cell is defined by a configuration (or gene) and all the genes in the array, each associated with a pair of coordinates, make up the blueprint (or genome) of the artificial organism. In the second part of the project, we add to the basic cell a memory and an interpreter to, respectively, store and decode the complete genome. The interpreter extracts from the genome the gene of a particular cell as a function of its position in the array (its coordinates) and thus determines the exact configuration of the relative multiplexer. The considerable redundancy introduced by the presence of a genome in each cell has significant advantages: self-replication (the automatic production of one or more copies of the original organism) and self-repair (the automatic repair of one or more faulty cells) become relatively simple operations. The multiplexer-based FPGA cell and the interpreter are finally embedded into an electronic module; an array of such modules make it possible to demonstrate self-repair and self-replication     

A Novel Built-In Self-Repair Approach for Embedded RAMs

In this paper, a novel built-in self-repair approach, block-level reconfiguration architecture, is proposed. Our approach is based on the concept of divided word line (DWL) for high-capacity memories, including SRAMs and DRAMs. This concept is widely used in low-power memory designs. However, the characteristics of divided word line memories have not been used for fault-tolerant applications. Therefore, we propose the block_repair fault-tolerant architecture based on the structure of DWL for high-capacity memories. The redundant rows of a memory array are divided into blocks and reconfiguration is performed at the block level instead of the traditional row level. Our fault-tolerant architecture can improve the yield for memory fabrication significantly. Moreover, the characteristics of low power and fast access time of DWL memories are also preserved. The reconfiguration mechanism of our block_repair architecture requires negligible hardware overhead. According to experimental results, the hardware overheads are less than 0.73% and 0.48% for 256-Kbit SRAMs and 8-Mbit DRAMs, respectively. The repair rate of our approach with previous memory repair algorithms is compared. It is found that block_repair approach improves repair rate significantly. The yield improvement over traditional row-based approaches is also analyzed. Simulated results show that the present approach can significantly improve fabrication yield.     

An on-line BIST RAM architecture with self-repair capabilities

The emerging field of self-repair computing is expected to have a major impact on deployable systems for space missions and defense applications, where high reliability, availability, and serviceability are needed. In this context, RAM (random access memories) are among the most critical components. This paper proposes a built-in self-repair (BISR) approach for RAM cores. The proposed design, introducing minimal and technology-dependent overheads, can detect and repair a wide range of memory faults including: stuck-at, coupling, and address faults. The test and repair capabilities are used on-line, and are completely transparent to the external user, who can use the memory without any change in the memory-access protocol. Using a fault-injection environment that can emulate the occurrence of faults inside the module, the effectiveness of the proposed architecture in terms of both fault detection and repairing capability was verified. Memories of various sizes have been considered to evaluate the area-overhead introduced by this proposed architecture     

A long lifetime, low error rate RRAM design with self-repair module

Resistive random access memory (RRAM) is one of the promising candidates for future universal memory. However, it suffers from serious error rate and endurance problems. Therefore, exploring a technical solution is greatly demanded to enhance endurance and reduce error rate. In this paper, we propose a reliable RRAM architecture that includes two reliability modules: error correction code (ECC) and self-repair modules. The ECC module is used to detect errors and decrease error rate. The self-repair module, which is proposed for the first time for RRAM, can get the information of error bits and repair wear-out cells by a repair voltage. Simulation results show that the proposed architecture can achieve lowest error rate and longest lifetime compared to previous reliable designs.     

Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS

In nanoscaled technologies, increased inter-die and intra-die variations in process parameters can result in large number of parametric failures in an SRAM array, thereby, degrading yield. In this paper, we propose a self-repairing SRAM to reduce parametric failures in memory. In the proposed technique, on-chip monitoring of leakage current and/or delay of a ring oscillator is used to determine the inter-die process corner of an SRAM die. Depending on the inter-die Vt shift, the self-repair system selects the proper body bias to reduce parametric failures. Simulations using predictive 70-nm device show that the proposed self-repairing SRAM improves design yield by 5%-40%. A test-chip is designed and fabricated in IBM 0.13-mum CMOS technology to successfully demonstrate the operation of the self-repair system.     

A CMOS gate array architecture for digital signal processingapplications

A new CMOS gate array architecture for digital signal processing (DSP) is presented. The basic cell structure takes into account the high degree of regularity of DSP datapaths. Therefore, it supports in particular the implementation of systolic arrays in connection with a pipelining scheme of one addition per half clock cycle. Together with a new gate array approach (macrocell design style), macrocells can be implemented efficiently on the new architecture. All DSP macrocells use dynamic transmission gate latches. Furthermore, the routing is done exclusively by cell abutment which results in short intercell routing. The macrocell design style is compared with the conventional gate array approach. In the common gate array approach, conventional gate array architectures are used together with conventional design equipment and layout strategies. The comparison shows a reduction in area and power consumption by a factor of 2.5 and 3.7, respectively. The efficiency increases by a factor of at least nine. These results were proved by analog circuit simulations and test chip measurements     

A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed