CMOS design technique to eliminate the stuck-open fault problem of testability

A dynamic CMOS design style is described, which utilises both N-type and P-type logic blocks and avoids the problems in generating tests for stuck-open faults. The testability of the resultant logic is examined analytically and fault simulation results are presented.     

A neural network algorithm for testing stuck-open faults in CMOS combinational circuits

In this article, an automatic test pattern generation technique using neural network models for stuck-open faults in CMOS combinational circuits is presented. For a gate level fault model of stuck-open faults in CMOS circuits, SR(slow-rise) and SF(slow-fall) gate transition faults we develop a neural network representation. A neural network computation technique for generating robust test patterns for stuck-open faults is given. The main result is extending previous efforts in stuck-at test pattern generation to stuck-open test pattern generation using neural network models. A second result is an extension of the technique to robust test pattern generation.     

Testable design of BiCMOS circuits for stuck-open fault detectionusing single patterns

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults     

Design for testability and DC test of switched-capacitor circuits

The authors present a design for testability (DFT) technique for switched-capacitor circuits. The principle is to reconfigure the SC circuit so that it realises a cascade of DC voltage amplifiers in which all capacitors are represented in a simple form. Then, the transfer function becomes a product of the ratio of two capacitors and the sensibility of the DC gain to each capacitor is close to unity. Consequently, a simple test with partial diagnosis is realised with some DC voltage stimuli and gives an accurate test result at the output of the last voltage amplifier     

A stuck fault model for dynamic CMOS combinational circuits

This paper utilizes the logic transistor function (LTF), that was devised to model the static CMOS combinational circuits at the transistor and logic level, to model the dynamic CMOS combinational circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault-free LTF using a systematic procedure. The model assumes the following logic values (0, 1, I, M), where I, and M imply an indeterminate logical value, and a memory element, respectively. The model is found to be efficient in describing a cluster of dynamic CMOS circuits at both the fault-free and faulty modes of operation. Both single and multiple transistor stuck faults are precisely described using this model. The classical stuck-at and non classical stuck open and short faults are analyzed. A systematic procedure to produce the fault-free and faulty LTFs for different implementations of the dynamic CMOS combinational circuits is presented.     

CMOS circuit testability

CMOS circuits present unique testing problems. Although open faults in CMOS circuits can be statistically tested, a sequence of patterns is required to guarantee a test. In addition, connections in the circuit layout affect testability. An automatic test generator has been developed to generate test sequences which will detect open CMOS faults.     

Exact probabilistic testability measures for multi-output circuits

The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the X-gate, and applying to the resulting graph the analysis based on supergates.     

Design of CMOS three-stage amplifiers for fast-settling switched-capacitor circuits

In this paper, a time-domain design procedure for fast-settling three-stage amplifiers is presented. In the proposed design approach, the amplifier is designed to settle within a specific time with a given settling accuracy and circuit noise budget by optimizing both the power consumption and silicon die area. Both linear and nonlinear settling regions of three-stage amplifiers are considered and optimal values of the amplifier stages transconductance and compensation capacitors are obtained using the genetic algorithm optimization. Detailed design equations are provided and circuit level simulation results using a 90 nm CMOS technology are presented to evaluate the usefulness of the proposed design scheme respected to the previously reported design approaches.     

DESIGN OF SYMMETRIC TERNARY CURRENT-MODE CMOS CIRCUITS

By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.     

CMOS异或电路的设计与应用

设计了四种CMOS"异或"单元电路,通过模拟仿真分析了它们各自的性能特点,并讨论了它们在奇偶检测电路、微处理器系统加法器电路以及单片机全加电路等设计中的不同应用.     

Design considerations for CMOS digital circuits with improvedhot-carrier reliability

The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled. Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated. The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F) and the transistor aspect ratio (τ) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging. Also, a number of simple design rules based on device geometry, circuit topology and power supply voltage are presented to ensure hot-carrier reliability     

Multifault and delay-fault testability of multilevel circuits

This paper investigates the relationship between test sets for multiple stuck-at faults and robust path-delay-fault tests in multilevel combinational circuits. It is shown that, in multilevel circuits, a complete robust path-delay-fault test set may not detect all multiple stuck-at faults. We also show that the detectability of the former does not imply the detectability of the latter, as suggested in a recent paper. The presence of undetectable or untested multiple stuck-at faults may invalidate some path delay tests.Supported in part by NSF Grant MIP-9320886.     

Improving path delay testability of sequential circuits

We analyze the causes of low path delay fault coverage in synchronous sequential circuits and propose a method to improve testability. The three main reasons for low path delay fault coverage are found to be: (A) combinationally false (nonactivatable) paths; (B) sequentially nonactivatable paths; and (C) unobservable fault effects. Accordingly, we classify undetected faults in Groups A, B, and C. Combinationally false paths ran be made testable by modifying the circuit or resynthesizing the combinational logic as discussed by other researchers. A majority of the untestable faults are, however found in Group B, where a signal transition cannot be functionally propagated through a combinational path. A test requires two successive states necessary to create a signal transition and propagate it through the target path embedded in the sequential circuit. We study a partial scan technique in which flip-flops are scanned to break cycles and shun that a substantial increase in the coverage of path delay faults is possible     

Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits

The possibility to perform realistic fault simulations for Silicon-On-Insulator circuits is investigated. A simple but complete fault simulation model (fsm) for a technology specific effect is described. The effect considered known as kink effect is typical for partially depleted devices but can occur in the presence of a floating body or in the sub-threshold region even in fully depleted devices causing wrong performances. The model proposed here comprises of only a single additional transistor with a controlled body current. It is not a real physical transistor but just one to describe the electrical behaviour of the device when the critical kink-effect situation occurs and for this reason does not increase the simulation time. From the comparison with device characterization measurements on a 1 μm technology device a good matching with the fsm was found.     

A realistic defect oriented testability methodology for analog circuits

Owing to the non-binary nature of their operation, analog circuits are influenced by process defects in a different manner compared to digital circuits. This calls for a careful investigation into the occurrence of defects in analog circuits, their modeling related aspects and their detection strategies. In this article, we demonstrate with the help of a real CMOS circuit that simple test stimuli, like DC, transient and AC, can detect most of the modeled process defects. Silicon devices tested with the proposed test methodology demonstrate the effectiveness of the method. Subsequently, the proposed test method is implemented in production test environment along with the conventional test for a comparative study. This test methodology is structured and simpler, therefore results in substantial test cost reduction.     

A design for testability approach for nano-CMOS analogue integrated circuits

Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). This article presents two designs for testability and fault diagnosis techniques using a new design analogue checker circuit in order to improve the testability and the diagnosability of nano-CMOS (complementary metal oxide semiconductor) analogue circuits used in safety-critical applications based on the system-on-chip (SoC) approach design. The testing techniques presented in this work can be done during and after the system fabrication. The checker is implemented in full-custom 65 nm Complementary metal–oxide–semiconductor (CMOS) technology with low supply voltage and small-size capabilities. SPICE simulations of the post-layout extracted CMOS checker, which include all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checker.     

Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults

This work presents a design technique for CMOS static and dynamic checkers (to be used in self-checking circuits), that allows the detection of all internal single transistor stuck-on and bridging faults causing unacceptable degradations of the circuit dynamic performance (but not logical errors). Such a technique exploits simple voltage detector circuits to make sure that the intermediate faulty voltages inevitably produced by the faults of interest are always propagated at the checker output as logic errors.With the use of our technique, the main disadvantages of static checkers, so far preventing their use in practical applications, are overcome.The method has been applied to the particular case of two-rail (static as well as dynamic) checkers and its validity has been verified by means of electrical level simulations.     

Reverse-voltage protection methods for CMOS circuits

A number of circuit configurations for protection of CMOS circuits against erroneous connections to the surrounding world (e.g. reversal of the supply voltage) are suggested and analyzed. It is found that protection against any permutation of input connections, output connections, and supply voltage connections can be obtained. The design objective is to prevent permanent damage to the chip regardless of how it is connected. It has been found both analytically and experimentally that this design goal can be achieved     

Double-edge-triggered D-flip-flops for high-speed CMOS circuits

Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2-μm technology